[AK4627]
MS1278-J-02 2012/03
- 1 -
AK4627 4ch ADC 6ch DAC 24bit CODEC ADC
DAC AK4627 ADC
48 LQFP
4ch 24bit ADC
- 64
- : 96kHz
-
- /
- S/(N+D): 92dB ( )
- , S/N: 102dB ( ) 103dB ( )
- HPF
- I/F : , I
2
S, TDM
6ch 24bit DAC
- 128
- : 192kHz
- 24 8
-
- S/(N+D): 90dB
- , S/N: 106dB
- I/F : , (20bit,24bit), I
2
S, TDM
- (128 , 0.5dB )
-
- (32kHz, 44.1kHz, 48kHz )
-
TTL I/F
µP I/F: 3 , I
2
C
: 256fs, 384fs, 512fs (fs=32kHz ∼ 48kHz)
128fs, 192fs, 256fs (fs=64kHz ∼ 96kHz)
128fs (fs=120kHz~ 192kHz)
: 4.5 ∼ 5.5V
: 2.7 ∼ 5.5V
: 48 LQFP
High Performance Multi-channel Audio CODEC
AK4627
[AK4627]
MS1278-J-02 2012/03
- 2 -
■
Audio
I
/
F
LPF
DAC
DATT
LPF DAC
DATT
LPF DAC DATT
LPF DAC DATT
LOUT1
ROUT1
LOUT2
ROUT2
AK4627
ADC HPF
ADC HPF
LIN1+/LIN1
LRCK
BICK
SDTI1
SDTI2
SDTI3
MCLK
LRCK
BICK
SDIN1
SDIN2
SDIN3
MCLK
LPF
DAC
DATT
LPF DAC
DATT
LOUT3
ROUT3
ADC
HPF
ADC
HPF
SDTO1
SDTO1
SDTO2
SDTO2
LIN1-
RIN1+/RIN1
RIN1-
LIN2+/LIN2
LIN2-
RIN2+/RIN2
RIN2-
[AK4627]
MS1278-J-02 2012/03
- 3 -
■
AK4627VQ -40 ∼ +105°C 48pin LQFP(0.5mm pitch)
AKD4627
■
VSS2
37
LIN1+/LIN1
36
38 RIN2+/RIN2
39
LIN2-
40 LIN2+/LIN2
41 RIN1-
42
43
RIN1+/RIN1
44
LIN1-
45 TST1
46
SGL
47
A
VDD
35
34
33
32
31
30
29
28
27
26
1
CAD1
2
PS
3
SDTO1 4
SDTO2 5
TVDD 6
DVDD 7
VSS1 8
TDM0/SDA/CDTI 9
DIF1/SCL/CCLK
10
DIF0/CSN
11
23
22
21
20
19
18
17
16
15
14
13
LRCK
BICK
MCLK
Top View
DZFE
48
PDN
12
24
25
SMUTE
RIN2-
AK4627
SDTI2
SDTI1
TST3
SDTI3
I2C/TST6
DFS0
TST2
TST4
TST5
LOUT1
ROUT2
LOUT2
ROUT3
LOUT3
DZF2
DZF1
VREFH
VCOM
ROUT1
CAD0
[AK4627]
MS1278-J-02 2012/03
- 4 -
No. Pin Name I/O Function
1 CAD0 I Chip Address 0 Pin
2 CAD1 I Chip Address 1 Pin
3
PS I Parallel/Serial Select Pin
“L”: Serial control mode, “H”: Parallel control mode
4 SDTO1 O ADC1 Audio Serial Data Output Pin
5 SDTO2 O ADC2 Audio Serial Data Output Pin
6
TVDD -
Output Buffer Power Supply Pin, 2.7V∼5.5V
7
DVDD -
Digital Power Supply Pin, 4.5V∼5.5V
8 VSS1 - Digital Ground Pin, 0V
TDM0 I TDM I/F Format Mode Pin in parallel control mode
“L”: Normal mode, “H”: TDM mode
9
SDA/CDTI I/O Control Data Input Pin in serial control mode
I2C pin= “L”: CDTI (3-wire Serial), I2C pin= “H”: SDA (I
2
C Bus)
DIF1 I Audio Data Interface Format 1 Pin in parallel control mode
10
SCL/CCLK I Control Data Clock Pin in serial control mode
I2C pin= “L”: CCLK (3-wire Serial), I2C pin= “H”: SCL (I
2
C Bus)
DIF0 I Audio Data Interface Format 0 Pin in parallel control mode
11
CSN I Chip Select Pin in 3-wire serial control mode
This pin should be connected to DVDD at I
2
C bus control mode
12
PDN I Power-Down & Reset Pin
When “L”, the AK4627 is powered-down and the control registers are reset to default
state. If the state of the PS pin or CAD1-0 pins change, then the AK4627 must be reset
by the PDN pin.
13 MCLK I Master Clock Input Pin
14 BICK I Audio Serial Data Clock Pin
15 LRCK I Input Channel Clock Pin
16 SDTI1 I DAC1 Audio Serial Data Input Pin
17 SDTI2 I DAC2 Audio Serial Data Input Pin
18 SDTI3 I DAC3 Audio Serial Data Input Pin
19
TST3 I Test Pin
This pin should be connected to VSS1
20
DFS0 I Double Speed Sampling Mode Pin (
Note 1)
“L”: Normal Speed, “H”: Double Speed
I2C I Control Mode Select Pin (PS pin = “L”)
“L”: 3-wire Serial, “H”: I
2
C Bus
21
TST6 I Test Pin (PS pin = “H”)
This pin should be connected to VSS1
22
TST2 Test Pin
This pin should be connected to VSS1.
23
TST4 Test Pin
This pin should be open.
24
TST5 Test Pin
This pin should be open.
25 LOUT3 O DAC3 Lch Analog Output Pin
26 ROUT3 O DAC3 Rch Analog Output Pin
27 LOUT2 O DAC2 Lch Analog Output Pin
28 ROUT2 O DAC2 Rch Analog Output Pin
29 LOUT1 O DAC1 Lch Analog Output Pin
30 ROUT1 O DAC1 Rch Analog Output Pin
[AK4627]
MS1278-J-02 2012/03
- 5 -
No. Pin Name I/O Function
31
VCOM O Common Voltage Output Pin, AVDD/2
Large external capacitor around 2.2μF is used to reduce power-supply noise.
32 VREFH I Positive Voltage Reference Input Pin, AVDD
33
AVDD -
Analog Power Supply Pin, 4.5V∼5.5V
34 VSS2 - Analog Ground Pin, 0V
35 DZF1
O
Zero Input Detect 1 Pin (
Note 2)
When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data,
this pin goes to “H”. And when RSTN bit is “0”, PWDAN pin is “L”, this pin goes to
“H”. It always is in “L” when the PS pin is “H”.
36 DZF2
O
Zero Input Detect 2 Pin (
Note 2)
When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data,
this pin goes to “H”. And when RSTN bit is “0”, PWDAN pin is “L”, this pin goes to
“H”. It always is in “L” when the PS pin is “H”.
37 RIN2- I ADC2 Rch Analog Negative Input Pin (SGL pin = “L”)
RIN2+ I ADC2 Rch Analog Positive Input Pin (SGL pin = “L”) 38
RIN2 I ADC2 Rch Analog Input Pin (SGL pin = “H”)
39 LIN2- I ADC2 Lch Analog Negative Input Pin (SGL pin = “L”)
LIN2+ ADC2 Lch Analog Positive Input Pin (SGL pin = “L”) 40
LIN2 I ADC2 Lch Analog Input Pin (SGL pin = “H”)
41 RIN1- I ADC1 Rch Analog Negative Input Pin (SGL pin = “L”)
RIN1+ I ADC1 Rch Analog Positive Input Pin (SGL pin = “L”)
42
RIN1 I ADC1 Rch Analog Input Pin (SGL pin = “H”)
43 LIN1- I ADC1 Lch Analog Negative Input Pin (SGL pin = “L”)
LIN1+ I ADC1 Lch Analog Positive Input Pin (SGL pin = “L”) 44
LIN1 I ADC1 Lch Analog Input Pin (SGL pin = “H”)
45 TST1 I Test Pin
This pin should be connected to VSS1.
46 SGL I Single-ended Input Mode Select Pin.
“L”: ADC Differential Input Mode
“H”: ADC Single-ended Input Mode
47 DZFE I Zero Input Detect Enable Pin
“L”: mode 7 (disable) at parallel mode,
zero detect mode is selectable by DZFM3-0 bits at serial mode
“H”: mode 0 (DZF1 is AND of all six channels)
48 SMUTE I Soft Mute Pin (Note 1)
When this pin goes to “H”, soft mute cycle is initialized.
When returning to “L”, the output mute releases.
Note 1. PS pin= “L” SMUTE, DFS0 pin OR
Note 2. PS pin= “L” DZFE = “L” (DZF1/2 pin)
DZFM3-0 bit (
Table 11)
Note 3.
[AK4627]
MS1278-J-02 2012/03
- 6 -
(VSS1=VSS2=0V; Note 4)
Parameter Symbol min max Unit
Power Supplies Analog
Digital
Output buffer
AVDD
DVDD
TVDD
-0.3
-0.3
-0.3
6.0
6.0
6.0
V
V
V
Input Current (any pins except for supplies) IIN -
±10
mA
Analog Input Voltage VINA -0.3 AVDD+0.3 V
Digital Input Voltage VIND -0.3 DVDD+0.3 V
Ambient Temperature (power applied) (Note 6) Ta -40 105
°C
Storage Temperature Tstg -65 150
°C
Note 4.
Note 5. VSS1 VSS2
Note 6. 100%
:
(VSS1=VSS2=0V; Note 4)
Parameter Symbol min typ max Unit
Power Supplies
(
Note 7)
Analog
Digital
Output buffer
AVDD
DVDD
TVDD
4.5
4.5
2.7
5.0
5.0
5.0
5.5
5.5
5.5
V
V
V
Note 4.
Note 7. AVDD, DVDD, TVDD I2C
ON AK4627 OFF
:
[AK4627]
MS1278-J-02 2012/03
- 7 -
(Ta=25°C; AVDD=DVDD=TVDD=5V; VSS2=VSS1=0V; VREFH=AVDD; fs=48kHz; BICK=64fs;
Signal Frequency=1kHz; 24bit Data; Measurement Frequency=20Hz∼20kHz at 48kHz, 20Hz~40kHz at fs=96kHz,
20Hz~40kHz at fs=192kHz; unless otherwise specified)
Parameter min typ max Unit
ADC Analog Input Characteristics (Single-ended Inputs)
Resolution 24 Bits
S/(N+D) (-0.5dBFS) fs=48kHz
fs=96kHz
84
-
96
92
dB
dB
DR (-60dBFS) fs=48kHz, A-weighted
fs=96kHz
fs=96kHz, A-weighted
94
88
93
102
99
105
dB
dB
dB
S/N (Note 11) fs=48kHz, A-weighted
fs=96kHz
fs=96kHz, A-weighted
94
88
93
102
99
105
dB
dB
dB
Interchannel Isolation 90 110 dB
DC Accuracy (Single-ended Inputs)
Interchannel Gain Mismatch 0.2 0.3 dB
Gain Drift 20 -
ppm/°C
Input Voltage AIN=0.68xVREFH 3.2 3.4 3.6 Vpp
fs=48kHz 10 14
kΩ
Input Resistance
fs=96kHz 11
kΩ
Power Supply Rejection (Note 9) 50 dB
ADC Analog Input Characteristics (Differential inputs)
84 96 dB S/(N+D) (-0.5dBFS) fs=48kHz
fs=96kHz
- 94 dB
95 103 dB
89 100 dB
DR (-60dBFS) fs=48kHz, A-weighted
fs=96kHz
fs=96kHz, A-weighted
94 106 dB
95 103 dB
89 100 dB
S/N (Note 11) fs=48kHz, A-weighted
fs=96kHz
fs=96kHz, A-weighted
94 106 dB
Interchannel Isolation 90 110 dB
DC Accuracy (Differential inputs)
Interchannel Gain Mismatch 0.2 0.3 dB
Gain Drift 20 -
ppm/°C
Input Voltage AIN=0.68xVREFH (Note 8) ±3.2 ±3.4 ±3.6 Vpp
fs=48kHz 22 32 kΩ
Input Resistance
fs=96kHz 19 kΩ
Power Supply Rejection (Note 9) 50 - dB
Common Mode Rejection Ratio (CMRR) (Note 10) 60 dB
[AK4627]
MS1278-J-02 2012/03
- 8 -
DAC Analog Output Characteristics
Resolution 24 Bits
S/(N+D) (0dBFS) fs=48kHz
fs=96kHz
fs=192kHz
80
78
-
98
98
98
dB
dB
dB
DR (-60dBFS) fs=48kHz, A-weighted
fs=96kHz
fs=96kHz, A-weighted
fs=192kHz
fs=192kHz, A-weighted
95
88
94
-
-
106
100
106
100
106
dB
dB
dB
dB
dB
S/N (Note 12) fs=48kHz, A-weighted
fs=96kHz
fs=96kHz, A-weighted
fs=192kHz
fs=192kHz, A-weighted
95
88
94
-
-
106
100
106
100
106
dB
dB
dB
dB
dB
Interchannel Isolation 90 110 dB
DC Accuracy
Interchannel Gain Mismatch 0.2 0.5 dB
Gain Drift 20 -
ppm/°C
Output Voltage AOUT=0.6xVREFH 2.75 3.0 3.25 Vpp
Load Resistance 5
kΩ
Load Capacitance 25 pF
Power Supply Rejection (Note 10) 50 dB
Note 8. (LIN+) – (LIN-) (RIN+) – (RIN-) VREFH
Note 9. VREFH +5V AVDD, DVDD, TVDD 1kHz, 50mVpp
Note 10. VREFH +5V LIN+(RIN+) LIN-(RIN-) AVDD1, 2 x 1/2 1.52Vpp, 1kHz
CMRR 1.52Vpp=-7dBFS
Note 11. CCIR-ARM 98dB(@fs=48kHz)
Note 12. CCIR-ARM 102dB(@fs=48kHz)
Parameter min typ max Unit
Power Supplies
Power Supply Current (AVDD+DVDD+TVDD)
Normal Operation (PDN = “H”)
AVDD fs=48kHz, 96kHz
fs=192kHz
DVDD+TVDD fs=48kHz (
Note 13)
fs=96kHz
fs=192kHz
Power-down mode (PDN = “L”) (
Note 14)
57
34
19
27
27
80
86
51
29
40
40
200
mA
mA
mA
mA
mA
μA
Note 13. TVDD=0.1mA(typ).
Note 14. VSS1
[AK4627]
MS1278-J-02 2012/03
- 9 -
(Ta=25°C; AVDD=DVDD=4.5∼5.5V; TVDD=2.7∼5.5V; fs=48kHz)
Parameter Symbol min typ max Unit
ADC Digital Filter (Decimation LPF):
Passband (Note 15)
±0.1dB
-0.2dB
-3.0dB
PB 0
-
-
20.0
23.0
18.9
-
-
kHz
kHz
kHz
Stopband SB 28 kHz
Passband Ripple PR
±0.04
dB
Stopband Attenuation SA 68 dB
Group Delay (Note 16) GD 16 1/fs
Group Delay Distortion
ΔGD
0
μs
ADC Digital Filter (HPF):
Frequency Response (Note 15) -3dB
-0.1dB
FR 1.0
6.5
Hz
Hz
DAC Digital Filter:
Passband (Note 15) -0.1dB
-6.0dB
PB 0
-
24.0
21.8
-
kHz
kHz
Stopband SB 26.2 kHz
Passband Ripple PR
±0.02
dB
Stopband Attenuation SA 54 dB
Group Delay (Note 16) GD 19.2 1/fs
DAC Digital Filter + Analog Filter:
Frequency Response: 0 ∼ 20.0kHz
40.0kHz (
Note 17)
80.0kHz (
Note 17)
FR
FR
FR
±0.2
±0.3
±1.0
dB
dB
dB
Note 15. fs -0.1dB 21.8kHz 0.454 x fs
Note 16. 24
ADC DAC 20/24
DAC
Note 17. 40.0kHz; fs=96kHz , 80.0kHz; fs=192kHz.
DC
(Ta=25°C; AVDD=DVDD=4.5∼5.5V; TVDD=2.7∼5.5V)
Parameter Symbol min typ max Unit
High-Level Input Voltage
Low-Level Input Voltage
VIH
VIL
2.2
-
-
-
-
0.8
V
V
High-Level Output Voltage
(SDTO1-2 pins: Iout=-100μA)
(DZF1, DZF2 pins: Iout=-100μA)
Low-Level Output Voltage
(SDTO1-2, DZF1, DZF2 pins: Iout= 100μA)
(SDA pin: Iout= 3mA)
VOH
VOH
VOL
VOL
TVDD-0.5
AVDD-0.5
-
-
-
-
-
-
-
-
0.5
0.4
V
V
V
V
Input Leakage Current Iin - - ±10 μA
[AK4627]
MS1278-J-02 2012/03
- 10 -
(Ta=25 ; AVDD= DVDD=4.5∼5.5V; TVDD=2.7∼5.5V; C
L
=20pF)
Parameter Symbol min typ max Unit
Master Clock Timing
256fsn, 128fsd:
Pulse Width Low
Pulse Width High
384fsn, 192fsd:
Pulse Width Low
Pulse Width High
512fsn, 256fsd, 128fsq:
Pulse Width Low
Pulse Width High
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
8.192
27
27
12.288
20
20
16.384
15
15
12.288
18.432
24.576
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
LRCK Timing
Normal mode (TDM0= “0”, TDM1= “0”)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Duty Cycle
fsn
fsd
fsq
Duty
32
64
128
45
48
96
192
55
kHz
kHz
kHz
%
TDM256 mode (TDM0= “1”, TDM1= “0”)
LRCK frequency
“H” time
“L” time
fsn
tLRH
tLRL
32
1/256fs
1/256fs
48
kHz
ns
ns
TDM128 mode (TDM0= “1”, TDM1= “1”)
LRCK frequency
“H” time
“L” time
fsd
tLRH
tLRL
64
1/128fs
1/128fs
96
kHz
ns
ns
Audio Interface Timing
Normal mode (TDM0= “0”, TDM1= “0”)
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “↑” (
Note 18)
BICK “↑” to LRCK Edge (
Note 18)
LRCK to SDTO1-2 (MSB)
BICK “↓” to SDTO1-2
SDTI1-3 Hold Time
SDTI1-3 Setup Time
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
tSDH
tSDS
81
32
32
20
20
20
20
40
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TDM256 mode (TDM0= “1”, TDM1= “0”)
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “↑” (
Note 18)
BICK “↑” to LRCK Edge (
Note 18)
BICK “↓” to SDTO1
SDTI1 Hold Time
SDTI1 Setup Time
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSD
tSDH
tSDS
81
32
32
20
20
10
10
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
TDM128 mode (TDM0= “1”, TDM1= “1”)
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “↑” (
Note 18)
BICK “↑” to LRCK Edge (
Note 18)
BICK “↓” to SDTO1
SDTI1-2 Hold Time
SDTI1-2 Setup Time
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSD
tSDH
tSDS
81
32
32
20
20
10
10
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 18. LRCK BICK
[AK4627]
MS1278-J-02 2012/03
- 11 -
Parameter Symbol min typ max Unit
Control Interface Timing (3-wire Serial mode):
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
200
80
80
40
40
150
50
50
ns
ns
ns
ns
ns
ns
ns
ns
Control Interface Timing (I
2
C Bus mode):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (
Note 19)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
Capacitive load on bus
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
Cb
-
1.3
0.6
1.3
0.6
0.6
0
0.1
-
-
0.6
0
-
400
-
-
-
-
-
-
-
1.0
0.3
-
50
400
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
pF
Power-down & Reset Timing
PDN Pulse Width (
Note 20)
PDN “↑” to SDTO1-2 valid (
Note 21)
tPD
tPDV
150
522
ns
1/fs
Note 19. 300ns(SCL )
Note 20. PDN pin “L” “H”
Note 21. PDN pin LRCK
Note 22. I
2
C-bus NXP B.V.
[AK4627]
MS1278-J-02 2012/03
- 12 -
■
1/fCLK
tCLKL
VIH
tCLKH
MCLK
VIL
1/fsn, 1/fsd
LRCK
VIH
VIL
tBCK
tBCKL
VIH
tBCKH
BICK
VIL
(TDM0 bit= “0”)
1/fCLK
tCLKL
VIH
tCLKH
MCLK
VIL
1/fs
LRCK
VIH
VIL
tLRLtLRH
tBCK
tBCKL
VIH
tBCKH
BICK
VIL
(TDM0 bit= “1”)
[AK4627]
MS1278-J-02 2012/03
- 13 -
tLRB
LRCK
VIH
BICK
VIL
tLRS
SDTO
50%TVDD
tBSD
VIH
VIL
tBLR
tSDS
SDTI
VIH
VIL
tSDH
(TDM0 bit= “0”)
tLRB
LRCK
VIH
BICK
VIL
SDTO 50%TVDD
tBSD
VIH
VIL
tBLR
tSDS
SDTI
VIH
VIL
tSDH
(TDM0 bit= “1”)
[AK4627]
MS1278-J-02 2012/03
- 14 -
tCSS
CSN
VIH
CCLK
VIL
VIH
CDTI
VIL
VIH
VIL
C1 C0 R/W A4
tCCKL tCCKH
tCDS tCDH
WRITE (3 )
CSN
VIH
CCLK
VIL
VIH
CDTI
VIL
VIH
VIL
D3 D2 D1 D0
tCSW
tCSH
WRITE (3 )
tHIGH
SCL
SDA
VIH
tLOW
tBUF
tHD:STA
tR
tF
tHD:DAT tSU:DAT tSU:STA
Stop Start Start Stop
tSU:STO
VIL
VIH
VIL
tSP
I
2
C
tPD
VIL
PDN
tPDV
SDTO
50%TVDD
VIH
[AK4627]
MS1278-J-02 2012/03
- 15 -
■
MCLK, LRCK, BICK MCLK LRCK
MCLK DFS0 pin DFS0, DFS1 bit (Manual
Setting Mode) (Auto Setting Mode) 2 Manual Setting Mode
(ACKS bit= “0”: Default) DFS0, DFS1 bit (
Table 1)
MCLK (
Table 2, Table 3, Table 4)
Auto Setting Mode (ACKS bit = “1”) MCLK (
Table 5)
(
Table 6) DFS bit
MCLK LRCK AK4627
VCOM (typ) MCLK LRCK
ON MCLK LRCK
DFS1 DFS0 Sampling Speed (fs)
0 0 Normal Speed Mode 32kHz~48kHz
(default)
0 1 Double Speed Mode 64kHz~96kHz
1 0 Quad Speed Mode 120kHz~192kHz
Table 1. (Manual Setting Mode)
LRCK MCLK (MHz) BICK (MHz)
fs 256fs 384fs 512fs 64fs
32.0kHz 8.1920 12.2880 16.3840 2.0480
44.1kHz 11.2896 16.9344 22.5792 2.8224
48.0kHz 12.2880 18.4320 24.5760 3.0720
Table 2. (Normal Speed Mode @Manual Setting Mode)
LRCK MCLK (MHz) BICK (MHz)
fs 128fs 192fs 256fs 64fs
88.2kHz 11.2896 16.9344 22.5792 5.6448
96.0kHz 12.2880 18.4320 24.5760 6.1440
Table 3. (Double Speed Mode @Manual Setting Mode)
( :Double Speed Mode (DFS1 bit= “0”, DFS0 bit= “1”) 128fs 192fs ADC )
LRCK MCLK (MHz) BICK (MHz)
fs 128fs 192fs 256fs 64fs
176.4kHz 22.5792 - - 11.2896
192.0kHz 24.5760 - - 12.2880
Table 4. (Quad Speed Mode @Manual Setting Mode)
( :Quad Speed Mode (DFS1 bit= “1”, DFS0 bit= “0”) ADC )
[AK4627]
MS1278-J-02 2012/03
- 16 -
MCLK Sampling Speed
512fs Normal
256fs Double
128fs Quad
Table 5. (Auto Setting Mode)
LRCK MCLK (MHz)
fs 128fs 256fs 512fs
Sampling
Speed
32.0kHz - - 16.3840
44.1kHz - - 22.5792
48.0kHz - - 24.5760
Normal
88.2kHz - 22.5792 -
96.0kHz - 24.5760 -
Double
176.4kHz 22.5792 - -
192.0kHz 24.5760 - -
Quad
Table 6. (Auto Setting Mode)
■ /
AK4627 SGL pin = “L” (Figure 1) “H” (Figure 2)
L/RIN1-2 pin L/RIN1-2 pin
L/RIN1-2 pin Open AK4627
SCF
L/RIN+
L/RIN-
LPF
LPF
AK4627
Figure 1. (SGL pin = “L”)
SCF
L/RIN
L/RIN-
LPF
AK4627
(Open)
Figure 2. (SGL pin = “H”)
[AK4627]
MS1278-J-02 2012/03
- 17 -
■
IIR 3 (32kHz, 44.1kHz, 48kHz) (50/15µs )
Double Speed Mode Quad Speed Mode OFF
DAC1(SDTI1), DAC2(SDTI2), DAC3(SDTI3)
Mode Sampling Speed DEM1 DEM0 DEM
0 Normal Speed 0 0 44.1kHz
1 Normal Speed 0 1 OFF
2 Normal Speed 1 0 48kHz
3 Normal Speed 1 1 32kHz
(default)
Table 7.
■ HPF
ADC DC HPF HPF fc fs=48kHz 1.0Hz
fs
[AK4627]
MS1278-J-02 2012/03
- 18 -
■
TDM1 bit = “0” TDM0 pin = “L” TDM1-0 bits = “00” 4 (
Table 8)
DIF1-0 bit MSB 2’s
SDTO1-2 BICK SDTI1-3 BICK
SDTI mode2, 3, 6, 7,10,11 16 ∼ 20 LSB “0”
LRCK BICK
Mode TDM 1 TDM0 DIF1 DIF0 SDTO1-2 SDTI1-3
0 0 0 0 0
24bit, Left
justified
20bit, Right
justified
H/L I
≥ 48fs
I
1 0 0 0 1
24bit, Left
justified
24bit, Right
justified
H/L I
≥ 48fs
I
2 0 0 1 0
24bit, Left
justified
24bit, Left
justified
H/L I
≥ 48fs
I
(default)
3 0 0 1 1 24bit, I
2
S 24bit, I
2
S L/H I
≥ 48fs
I
Table 8. ( )
TDM0 pin “H” TDM I/F SDTO1 pin ADC(4ch)
SDTO2 pin = “L” TDM256 Mode SDTI1 pin DAC(6ch) SDTI2-
3 BICK 256fs LRCK “H” “L” 1/256fs(min) 4
(
Table 9) DIF1-0 bit MSB 2’s
SDTO1 BICK SDTI1 BICK
TDM LOOP1-0 bit “0” TDM128 Mode (96kHz) TDM1
(
Table 10) SDTI1 pin DAC(4ch; L1, R1, L2, R2) SDTI2 pin DAC(2ch; L3, R3) 6ch
TDM256 TDM0 pin TDM0 “H” 2
TDM0 TDM1 “1”
LRCK BICK
Mode TDM 1 TDM0 DIF1 DIF0 SDTO1 SDTI1
4 0 1 0 0
24bit, Left
justified
20bit, Right
justified
↑
I 256fs I
5 0 1 0 1
24bit, Left
justified
24bit, Right
justified
↑
I 256fs I
6 0 1 1 0
24bit, Left
justified
24bit, Left
justified
↑
I 256fs I
7 0 1 1 1 24bit, I
2
S 24bit, I
2
S
↓
I 256fs I
Table 9. (TDM256 )
LRCK BICK
Mode TDM 1 TDM0 DIF1 DIF0 SDTO1 SDTI1,
SDTI2
8 1 1 0 0
24bit, Left
justified
20bit, Right
justified
↑
I 128fs I
9 1 1 0 1
24bit, Left
justified
24bit, Right
justified
↑
I 128fs I
10 1 1 1 0
24bit, Left
justified
24bit, Left
justified
↑
I 128fs I
11 1 1 1 1 24bit, I
2
S 24bit, I
2
S
↓
I 128fs I
Table 10. (TDM128 )
[AK4627]
MS1278-J-02 2012/03
- 19 -
LRCK
BICK
(
64fs
)
SDTO
(
o
)
0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0
23
1
22 0 23 22 12 11 10 0 23
SDTI
(
i
)
118 019 8 7 118 019 8 7
Lch Data Rch Data
Don’t Care Don’t Care
12 11 10
SDTO-23:MSB, 0:LSB; SDTI-19:MSB, 0:LSB
Figure 3. Mode 0
LRCK
BICK
(
64fs
)
SDTO
(
o
)
0 1 2 8 9 10 24 25 31 0 1 2 8 9 10 24 25 31 0
23
1
22 0 23 22 16 15 14 0 23
SDTI
(
i
)
122 023 8 7 122 023 8 7
23:MSB, 0:LSB
Lch Data Rch Data
Don’t Care Don’t Care
16 15 14
Figure 4. Mode 1
LRCK
BICK
(
64fs
)
SDTO
(
o
)
0 1 2 21 22 23 24 31 0 1 2 0
23
1
22 1 23 22 23
SDTI
(
i
)
22 23 0 2223
23:MSB, 0:LSB
Lch Data Rch Data
Don’t Care
2
2 1
28 29 30
23
0
22 23 24 31
1
0
Don’t Care
2
21
28 29 30
0
Figure 5. Mode 2
LRCK
BICK
(
64fs
)
SDTO
(
o
)
0 1 2 3 22 23 24 25 0 0 1
SDTI
(
i
)
3129 30
23 22 1
22 23 0
23:MSB, 0:LSB
Lch Data Rch Data
Don’t Care
2
2 1
0
2 3 22 23 24 25 031 29 30
23 22 1
2223 0
Don’t Care
2
21
0
1
Figure 6. Mode 3
[AK4627]
MS1278-J-02 2012/03
- 20 -
256 BICK
BICK(256fs)
SDTO1(o)
SDTI1(i)
22 0
L1
32 BICK
18 0
L1
32 BICK
18 0
R1
32 BICK
18 0
L2
32 BICK
18 0
R2
32 BICK
18 0
L3
32 BICK
18 0
R3
32 BICK
22 0
R1
32 BICK
22 23
19 19 19 19 19
23
19
23
19
LRCK
22 0
L2
22 0
R2
23 23
32 BICK 32 BICK
Figure 7. Mode 4
256 BICK
BICK(256fs)
SDTO1(o)
SDTI1(i)
22 0
L1
32 BICK
22 0
L1
32 BICK
22 0
R1
32 BICK
22 0
L2
32 BICK
22 0
R2
32 BICK
22 0
L3
32 BICK
22 0
R3
32 BICK
22 0
R1
32 BICK
22 23
23 23 23 23 23
23
23
23
23
LRCK
22 0
L2
32 BICK
22 0
R2
32 BICK
23 23
Figure 8. Mode 5
256 BICK
BICK(256fs)
SDTO1(o)
SDTI1(i)
22 0
L1
32 BICK
22 0
L1
32 BICK
22 0
R1
32 BICK
22 0
L2
32 BICK
22 0
R2
32 BICK
22 0
L3
32 BICK
22 0
R3
32 BICK
22 0
R1
32 BICK
22
22
23
23 23 23 23 23
23
23
23
23
LRCK
22 0
L2
32 BICK
22 0
R2
32 BICK
23 23
Figure 9. Mode 6
256 BICK
BICK(256fs)
SDTO1(o)
SDTI1(i)
23 0
L1
32 BICK
23 0
L1
32 BICK
23 0
R1
32 BICK
23 0
L2
32 BICK
23 0
R2
32 BICK
23 0
L3
32 BICK
23 0
R3
32 BICK
23 0
R1
32 BICK
23
23
LRCK
23 0
L2
32 BICK
23 0
R2
32 BICK
Figure 10. Mode 7
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