[AK4104]
MS0642-J-01 2010/09
- 1 -
AK4104 192kHz (DIT) AK4104 AES3,
IEC60958, S/PDIF, EIAJ CP1201 AK4104
8
192kHz
AES3, IEC60958, S/PDIF, EIAJ CP1201 &
42
: 128/192/256/384/512/768/1024/1536fs
: / /I
2
S
4 3
CMOS
: 2.7 ∼ 3.6V
: 16 TSSOP
Ta: -20 ∼ 85 °C
192kHz 24-Bit 3.3V DIT
AK4104
[AK4104]
MS0642-J-01 2010/09
- 2 -
■
LRCK
BICK
Audio
Data
Interface
MCLK
PDN
Prescaler
Biphase
Encoder
SDTI1
TX
CDTO
CSN
CCLK
CDTI
µP
Interface
VDD
VSS
Figure 1. AK4104 Block Diagram (MODE bit = “0”)
LRCK
BICK
Audio
Data
Interface
MCLK
PDN
Prescaler
Biphase
Encoder
SDTI1
TX
CSN
CCLK
CDTI
µP
Interface
VDD
VSS
SDTI2
Figure 2. AK4104 Block Diagram (MODE bit = “1”)
ASAHI KASEI [AK4104]
MS0642-J-01 2010/09
- 3 -
■
AK4104ET −20 ∼ +85°C 16pin TSSOP (0.65mm pitch)
AKD4104 AK4104
■
1
MCLK
LRC
K
BIC
K
CSN
CCL
K
CDTI
AK4104
Top
View
2
3
4
5
6
7
8
TX
VDD
CDTO/ SDTI2
VSS
TEST4
TEST3
TEST2
16
15
14
13
12
11
10
9
PDN
SDTI1
TEST1
ASAHI KASEI [AK4104]
MS0642-J-01 2010/09
- 4 -
No. Pin Name I/O Function
1 MCLK I Master Clock Input Pin
2 BICK I Audio Serial Data Clock Pin
3 SDTI1 I Audio Serial Data Input 1 Pin
4 LRCK I Input Channel Clock Pin
5 PDN I
Power Down and Reset Pin
“L”: Power down and Reset, “H”: Power up
6 CSN I Chip Select Pin
7 CCLK I Control Data Clock Pin
8 CDTI I Control Data Input Pin
9 TEST1 I
TEST Pin
This pin should be connected to VDD.
10 TEST2 O
TEST Pin
This pin should be OPEN.
11 TEST3 O
TEST Pin
This pin should be OPEN.
12 TEST4 O
TEST Pin
This pin should be OPEN.
13 VSS - Ground Pin
14 VDD -
Power Supply Pin, 2.7 ∼ 3.6V
CDTO O Control Data Output Pin, The output is “Hi-Z” when PDN pin = “L”.
15
SDTI2 I Audio Serial Data Input 2 Pin
16 TX O
Transmit Channel Output Pin, The output is “L” when PDN pin = “L” or RSTN bit
=“0” or PW bit = “0” or MCLK stops.
ASAHI KASEI [AK4104]
MS0642-J-01 2010/09
- 5 -
(VSS = 0V; Note 1)
Parameter Symbol min max Units
Power Supply VDD −0.3 4.6 V
Input Current, Any Pin Except Supplies IIN - ±10 mA
Digital Input Voltage (Note 2) VIND −0.3
VDD+0.
3
V
Ambient Temperature (Powered applied) Ta −20 85 °C
Storage Temperature Tstg −65 150 °C
Note 1.
Note 2. MCLK, BICK, SDTI1, LRCK, PDN, CSN, CCLK, CDTI, SDTI2
:
(VSS = 0V; Note 1)
Parameter Symbol min typ max Units
Power Supply VDD 2.7 3.3 3.6
V
Note 1.
:
DC
(Ta = 25°C; VDD = 2.7 ∼ 3.6V)
Parameter Symbol min typ max Units
Power Supply Current (Note 3)
Normal Operation (PDN pin = “H”, fs=44.1kHz) (
Note 3)
Full power-down mode (PDN pin = “L”) (
Note 4)
0.9
10
1.8
50
mA
μA
High-Level Input Voltage
Low-Level Input Voltage
VIH
VIL
70%VD
D
-
-
-
-
30%VD
D
V
V
High-Level Output Voltage (Iout=-80μA)
Low-Level Output Voltage (Iout=80µA)
VOH1
VOL1
VDD-0.4
-
-
-
-
0.4
V
V
Input Leakage Current Iin - -
± 10
µA
Note 3. TX pin: VDD = 3.3V
= 1.0mA(typ)@fs = 48kHz, 1.4mA(typ)@fs = 96kHz 2.6mA(typ)@fs = 192kHz
PDN= “L” VSS 10μA(typ)
TX pin: 20pF , VDD = 3.3V IDD = 3.3mA(typ)@fs = 192kHz
Note 4. VDD VSS
TX
(Ta = 25°C; VDD = 2.7 ∼ 3.6V)
Parameter Symbol min typ max Units
High-Level Output Voltage ( Iout=-400μA)
Low-Level Output Voltage ( Iout=400μA)
VOH2
VOL2
VDD-0.4
-
-
-
-
0.4
V
V
Load Capacitance CL - - 50 pF
ASAHI KASEI [AK4104]
MS0642-J-01 2010/09
- 6 -
(Ta = 25°C; VDD = 2.7 ∼ 3.6V, C
L
= 20pF)
Parameter Symbol min typ max Units
Master Clock Frequency
Frequency
Duty Cycle
fCLK
dCLK
2.048
40
36.864
60
MHz
%
LRCK Frequency
Frequency
Duty Cycle
fs
dCLK
8
45
192
55
kHz
%
Audio Interface Timing
BICK Period
BICK Pulse Width Low
Pulse Width High
BICK “↑” to LRCK Edge (
Note 5)
LRCK Edge to BICK “↑” (
Note 5)
SDTI Hold Time
SDTI Setup Time
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
81
30
30
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
CDTO Delay
CSN “↑” to CDTO Hi-Z
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tDCD
tCCZ
200
80
80
40
40
150
150
50
45
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Power-Down & Reset Timing
PDN Pulse Width (
Note 6)
tPD
150
ns
Note 5. LRCK BICK “↑”
Note 6. PDN pin = “L” AK4104
ASAHI KASEI [AK4104]
MS0642-J-01 2010/09
- 7 -
■
1/fCLK
tCLKL
VIH
tCLKH
MCLK
VIL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK
VIL
tBCK
tBCKL
VIH
tBCKH
BICK
VIL
Figure 3. Clock Timing
tLRB
LRCK
VIH
BICK
VIL
tSDS
VIH
SDTI
VIL
tSDH
VIH
VIL
tBLR
Figure 4. Serial Interface Timing
ASAHI KASEI [AK4104]
MS0642-J-01 2010/09
- 8 -
tCCKL
CSN
CCLK
tCDS
CDTI
tCDH
tCSS
C0 A4
tCCKH
CDTO
Hi-Z
R/W
C1
VIH
VIL
VIH
VIL
VIH
VIL
tCCK
Figure 5. WRITE/READ Command Input Timing in 3-wire/4-wire serial mode
tCSW
CSN
CCLK
CDTI D2 D0
tCSH
CDTO
Hi-Z
D1D3
VIH
VIL
VIH
VIL
VIH
VIL
Figure 6. WRITE Data Input Timing in 3-wire/4-wire serial mode
CSN
CCLK
tDCD
CDTO
D7 D6
CDTI
A1 A0
D5
Hi-Z
50%VDD
VIH
VIL
VIH
VIL
VIH
VIL
Figure 7. READ Data Output Timing 1 in 4-wire serial mode
ASAHI KASEI [AK4104]
MS0642-J-01 2010/09
- 9 -
CSN
CCLK
tCCZ
CDTO
D2 D1
CDTI
D0
D3
tCSW
tCSH
50%VDD
VIH
VIL
VIH
VIL
VIH
VIL
Hi-Z
Figure 8. READ Data Output Timing 2 in 4-wire serial mode
tPD
VIL
PDN
Figure 9. Power-Down & Reset Timing
ASAHI KASEI [AK4104]
MS0642-J-01 2010/09
- 11 -
■
BICK LRCK SDTI 4 (
Table 2) DIF1-0 pin
MSB 2’s complement BICK
Mode3 ≥ 48fs BICK=32fs LSB “0” 16bit,
I
2
S Compatible format
Mode DIF1 DIF0 SDTI Format BICK Figure
0 0 0 16bit, LSB justified
≥ 32fs
Figure 10
1 0 1 24bit, LSB justified
≥ 48fs
Figure 11
2 1 0 24bit, MSB justified
≥ 48fs
Figure 12
3 1 1 16/24bit, I
2
S Compatible
≥ 48fs or 32fs
Figure 13
Table 2. Audio Interface Format
LRCK
BICK(32fs)
0 1102 3 9 1112131415 0 123 10109 1112131415
SDTI(i)
Don't Care 1 0 15 14 13 21015 14 13 12 12Don't Care
SDTI-15:MSB, 0:LSB
SDTI(i)
15 14 13 7654321015 14 13 1576543210
BICK(64fs)
0 1182 3 19 20 31 0 1 2 3 1018 19 20 3117 17
Lch Data Rch Data
Figure 10. Mode 0 Timing
LRCK
BICK(64fs)
0 1 22431012 10312489 89
SDTI(i)
Don't Care 0 8 10
23:MSB, 0:LSB
Lch Data Rch Data
23 8 Don't Care 231
Figure 11. Mode 1 Timing
LRCK
BICK(64fs)
0 1 220212431012 102220 21 312422 23 23
SDTI(i)
Don't Care0 0
23:MSB, 0:LSB
Lch Data Rch Data
Don't Care
432123 22 23 22 231234
Figure 12. Mode 2 Timing
ASAHI KASEI [AK4104]
MS0642-J-01 2010/09
- 12 -
LRCK
BICK(64fs)
0 1 22521 24 0 12 1022 2521 2422 23 233
SDTI(i)
Don't Care0 0
23:MSB, 0:LSB
Lch Data Rch Data
Don't Care
432123 22 23 22 1234
Figure 13. Mode 3 Timing
■ DIT
AK4104 4 μP I/F (MODE bit = “0”) 3 μP I/F (MODE bit = “1”) 3
μP I/F SDTI1 SDTI2 data
MODE SEL1 SEL0 μP I/F DIT input
0 x x 4-wire SDTI1
1 0 0 3-wire SDTI1
1 0 1 3-wire SDTI2
1 1 0 3-wire SDTI2:DIT Bypass
1 1 1 Reserved
(x: Don’t care)
Table 3. DIT Input
ASAHI KASEI [AK4104]
MS0642-J-01 2010/09
- 13 -
■
TX Figure 14 192
2 32
2
0 1
Figure 15 16 8
Frame 191 Frame 0 Frame 1
Sub-frame Sub-frame
M
Channel 1 W Channel 2 B Channel 1 W Channel 2 M Channel 1 W Channel 2
Figure 14.
0 1 1 0 0 0 1 0
Figure 15.
Figure 16 0-3
3 (B) 0 1
1 (M) 0 1 2
(W) 2
Table 4 4-27 24
2 27 MSB 16 4-11
0 28 “H”
29 192
0 191 30
192 0
191 31 4-31
Sync P
C
UV
L M
S Audio sample S
B B
0 3 4 27 28 29 30 31
Figure 16.
(fs) 64
L A 1 R B
2 1
Preamble Preceding state = 0 Preceding state = 1
B 11101000 00010111
M 11100010 00011101
W 11100100 00011011
Table 4.
ASAHI KASEI [AK4104]
MS0642-J-01 2010/09
- 14 -
bit0 = “0” bits20-23(audio channel) CT20 bit CT20 bit = “1”
AK4104 bits20-23 = “1000” 2
bits20-23= “0100” CT20 bit = “0” 1 2
bits20-23= “0000”
■
AK4104 4 I/F (MODE bit = “0”) 3 I/F (MODE bit = “1”)
1. 4 (MODE bit = “0”,default)
4 I/F pin(CSN,CCLK,CDTI,CDTO) I/F
Chip address(2bits, C1/0; “11” ), Read/Write(1bit), Register address(MSB first, 5bits) Control
data(MSB first, 8bits) CCLK “↓” “↑”
CCLK 16 “↑” CCLK 16
CSN “H” CSN “↑” Hi-Z CCLK
5MHz (max) PDN pin= “L”
CDTI
CCLK
CSN
C1
0 1 2 34567
8 9 10 11 12 13 14 15
D4D5D6D7A1A2A3A4R/WC0 A0 D0 D1 D2 D3
CDTO
Hi-Z
WRITE
CDTI
C1 D4D5D6D7A1A2A3A4R/WC0 A0 D0 D1 D2 D3
CDTO
Hi-Z
READ
D4D5D6D7 D0 D1 D2 D3
Hi-Z
C1-C0: Chip Address: (Fixed to “11”)
R/W: READ/WRITE (0:READ, 1:WRITE)
A4-A0: Register Address
D7-D0: Control Data
Figure 17. 4-wire μP I/F Timing
*AK4104 (PDN pin = “L”) MCLK
ASAHI KASEI [AK4104]
MS0642-J-01 2010/09
- 15 -
2. 3 (MODE bit = “1”)
3 I/F pin(CSN,CCLK,CDTI) I/F Chip
address(2bits, C1/0; “11” ), Read/Write(1bit, “1” , ), Register address(MSB first, 5bits)
Control data(MSB first, 8bits) CCLK “↑” “↓”
CCLK 16 CCLK 16 CSN “H”
CCLK 5MHz (max) PDN pin= “L”
PDN pin = “L” RSTN bit
CDTI
CCLK
CSN
C1
0 1234567
8 9 10 11 12 13 14 15
D4D5D6D7A1A2A3A4R/WC0 A0 D0D1D2D3
C1-C0: Chip Address (Fixed to “11”)
R/W: READ/WRITE (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 18. 3-wire μP I/F Timing
*AK4104 3 Chip address C1/0 R/W “011”
*AK4104 (PDN pin = “L”) MCLK
ASAHI KASEI [AK4104]
MS0642-J-01 2010/09
- 16 -
■ Register Map
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Control 1 1 0 0 0 DIF1 DIF0 PW RSTN
01H Reserved 0 1 0 1 1 0 1 1
02H Control 2 0 0 0 0 0 MODE SEL1 SEL0
03H TX 1 0 0 0 0 0 V TXE
04H Channel Status Byte0 CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0
05H Channel Status Byte1 CS15 CS14 CS13 CS12 CS11 CS10 CS9 CS8
06H Channel Status Byte2 CS23 CS22 CS21 CS20 CS19 CS18 CS17 CS16
07H Channel Status Byte3 CS31 CS30 CS29 CS28 CS27 CS26 CS25 CS24
08H Channel Status Byte4 CS39 CS38 CS37 CS36 CS35 CS34 CS33 CS32
09H Channel Status Byte5 0 0 0 0 0 0 CS41 CS40
Notes:
0AH∼1FH
PDN pin = “L”
RSTN bit = “0” PW RSTN bit = “0”
“0” “0” “1” “1”
■
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Control 1 1 0 0 0 DIF1 DIF0 PW RSTN
R/W R/W
Default 1 0 0 0 1 1 1 1
RSTN:
0:
1:
PW:
0:
1:
DIF1-0: (
Table 2)
Default: “11”, Mode 3
ASAHI KASEI [AK4104]
MS0642-J-01 2010/09
- 17 -
Register Name D7 D6 D5 D4 D3 D2 D1 D0
02H Control 3 0 0 0 0 0 MODE SEL1 SEL0
R/W R/W
Default 0 0 0 0 0 0 0 0
MODE:
0: 4
1: 3
SEL1-0: DIT
00: SDTI1
01: SDTI2
10: SDTI2 (DIT Bypass)
11: Reserved
(NOTE) SEL1-0 bits 4 (MODE bit = “0”)
Register Name D7 D6 D5 D4 D3 D2 D1 D0
03H TX 1 0 0 0 0 0 V TXE
R/W R/W
Default 1 0 0 0 0 0 0 1
V:
0: Valid
1: Invalid
TXE: TX
0: “L”
1:
Register Name D7 D6 D5 D4 D3 D2 D1 D0
04H Channel Status Byte0 CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0
Default 0 0 0 0 0 1 0 0
05H Channel Status Byte1 CS15 CS14 CS13 CS12 CS11 CS10 CS9 CS8
Default 0 0 0 0 0 0 0 0
06H Channel Status Byte2 CS23 CS22 CS21 CS20 CS19 CS18 CS17 CS16
Default 0 0 0 0 0 0 0 0
07H Channel Status Byte3 CS31 CS30 CS29 CS28 CS27 CS26 CS25 CS24
Default 0 0 0 0 0 0 0 0
08H Channel Status Byte4 CS39 CS38 CS37 CS36 CS35 CS34 CS33 CS32
Default 0 0 0 0 0 0 0 0
09H Channel Status Byte5 0 0 0 0 0 0 CS41 CS40
Default 0 0 0 0 0 0 0 0
CS7-0: Transmitter Channel Status Byte 0
Default: “00000100”
CS39-8: Transmitter Channel Status Byte 4-1
Default: “00000000”
CS41-CS40: Transmitter Channel Status Byte 5
Default: “00000000”, D7-D2 bits should be written “1”.
ASAHI KASEI [AK4104]
MS0642-J-01 2010/09
- 18 -
Figure 19 Figure 20 4-wire serial mode 3-wire serial mode
(AKD4104)
MCLK
1
BICK
2
SDTI1
3
LRCK
4
PDN
5
CSN
6
CCLK
7
CDTI 8
TX
16
CDTO
15
VDD 14
VSS
13
TEST4
12
TEST3
11
TEST2
10
TEST1
9
Master Clock
AK4104
fs
24bit Audio Data
Reset & Power down
64fs
0.1u
+
A
nalog Suppl
y
2.7 to 3.6V
10u
Optic transmitting
module
Micro
Controller
Figure 19. Typical Connection Diagram (MODE bit = “0”, 4 wire mode )
MCLK
1
BICK
2
SDTI1
3
LRCK
4
PDN
5
CSN
6
CCLK
7
CDTI 8
TX
16
SDTI2
15
VDD 14
VSS
13
TEST4
12
TEST3
11
TEST2
10
TEST1
9
Master Clock
AK4104
fs
24bit Audio Data1
Reset & Power down
64fs
0.1u
+
A
nalog Suppl
y
2.7 to 3.6V
10u
Optic transmitting
module
Micro
Controller
24bit Audio Data2
Figure 20. Typical Connection Diagram (MODE bit = “1”, 3 wire mode )
ASAHI KASEI [AK4104]
MS0642-J-01 2010/09
- 19 -
0-10°
Detail A
Seating Plane
0.10
0.17±0.05
0.22±0.1
0.65
*5.0±0.1
1.1 (max)
A
1
8
9 16
16pin TSSOP (Unit: mm)
*4.4±0.1
6.4±0.2
0.5±0.2
0.1±0.1
NOTE: Dimension "*" does not include mold flash.
0.13
M
■
ASAHI KASEI [AK4104]
MS0642-J-01 2010/09
- 20 -
AKM
4104ET
XXYYY
1) Pin #1 indication
2) Date Code : XXYYY (5 digits)
XX: Lot#
YYY: Date Code
3) Marketing Code : 4104ET
4) Asahi Kasei Logo
Date (YY/MM/DD) Revision Reason Page Contents
07/10/15 00
10/09/28 01
19
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