AKM AK4113VF 仕様

ASAHI KASEI [AK4113]

MS0349-J-02 2005/08

- 1 -

AK4113 192kHz, 24bit (DIR)

Dolby Digital / MPEG Non-PCM

CODEC(AK4626, AK4628) Dolby Digital

µP I/F

AK4113 30Pin VSOP

* Dolby Digital is a trademark of Dolby Laboratories.

 AES/EBU, IEC60958, S/PDIF, EIAJ CP1201

 PLL

 PLL : 8k ∼ 216kHz

 PLL/X'tal

 6 1



 32kHz, 44.1kHz, 48kHz



- Non-PCM

- DTS-CD

-

8kHz, 11.025kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz,

64kHz, 88.2kHz, 96kHz, 176.4kHz, 192kHz

- Unlock & Parity Error

- Validity

- DAT Start ID

 24bit

 : /

 40bit

 Non-PCM Pc, Pd

 CD Q-subcode



µP : I

2

C(max. 400kHz) or 4-wire

 64fs/128fs/256fs/512fs

 : 2.7 to 3.6V 5V

 30 VSOP

 Ta: - 40 ∼ 85°C

6:1 192kHz 24bit DIR

AK4113

ASAHI KASEI [AK4113]

MS0349-J-02 2005/08

- 2 -

In

p

ut

Selecto

r

Clock

Recovery

Clock

Generato

r

DAIF

Decoder

A

C-3/MPEG

Detect

DEM

µP I/F

Audio

I/F

X'tal

Oscillato

r

PDN

INT0 P/SN= “L”

LRCK

BICK

SDTO

DAUX

MCKO2

XTOXTI

RAVDDAVSS

CDTI

CDTO

CCLK

CSN

DVDD

DVSS

TVDD

MCKO1

I2C

RX1

RX2

RX3

RX4

RX5

RX6

V/TX

Error &

Detect

STATUS

INT1

(

C, UOUT

)

Q-subcode

buffe

r

(

BOUT

)

Figure 1.

In

p

ut

Selecto

r

Clock

Recovery

Clock

Generato

r

DAIF

Decoder

A

C-3/MPEG

Detect

DEM

Audio

I/F

X'tal

Oscillato

r

PDN

INT0 P/SN=“H”

LRCK

BICK

SDTO

DAUX

MCKO2

XTOXTI

RAVDDAVSS

CM1

CM0

OCKS1

OCKS0

DVDD

DVSS

TVDD

MCKO1

RX1

RX5

DIF0

DIF1

DIF2

IPS

V

Error &

Detect

STATUS

INT1

FS96

Figure 2.

ASAHI KASEI [AK4113]

MS0349-J-02 2005/08

- 3 -



AK4113VF -40 ~ +85 °C 30pin VSOP (0.65mm pitch)

AKD4113 AK4113



6

5

4

3

2

1

DVDD

DVSS

V/TX

TVDD

XTI

XTO

PDN 7

R

8

Top

View

10

9

A

VDD

A

VSS

RX1

11

RX2/DIF0 12

13

14

RX3/DIF1

RX4/DIF2

CM0/CDTO/CAD1

CM1/CDTI/SDA

OCKS1/CCLK/SCL

OCKS0/CSN/CAD0

MCKO1

MCKO2

DAUX

BICK

SDTO

LRCK

INT0

FS96/I2C

25

26

27

28

29

30

24

23

21

22

20

19

18

17

P/SN

INT1

15

RX5

16

IPS/RX6

ASAHI KASEI [AK4113]

MS0349-J-02 2005/08

- 4 -

No. Pin Name I/O Function

1 DVDD - Digital Power Supply Pin, 3.3V

2 DVSS - Digital Ground Pin

3 TVDD - Input Buffer Power Supply Pin, 3.3V or 5V

V O Validity Flag Output Pin in parallel control mode

4

TX O Transmit channel (Through data) Output Pin in serial control mode

5 XTI I X'tal Input Pin

6 XTO O X'tal Output Pin

7 PDN I

Power-Down Mode Pin

When “L”, the AK4113 is powered-down and reset.

8 R -

External Resistor Pin

This pin must be connected to AVSS via 15kΩ ± 5% resistor.

9 AVDD - Analog Power Supply Pin

10 AVSS - Analog Ground Pin

11 RX1 I Receiver Channel #1 Pin (Internal Biased Pin)

DIF0 I Audio Data Interface Format #0 Pin in parallel control mode

12

RX2 I Receiver Channel #2 Pin in serial control mode (Internal Biased Pin)

DIF1 I Audio Data Interface Format #1 Pin in parallel control mode

13

RX3 I Receiver Channel #3 Pin in serial control mode (Internal Biased Pin)

DIF2 I Audio Data Interface Format #2 Pin in parallel control mode

14

RX4 I Receiver Channel #4 Pin in serial control mode (Internal Biased Pin)

15 RX5 I Receiver Channel #5 Pin (Internal Biased Pin)

IPS I Input Channel Select Pin in parallel control mode

16

RX6 I Receiver Channel #6 Pin (Internal Biased Pin)

Interrupt #1 Pin (when BCU bit = “0”)

U-bit Output Pin (when BCU bit = “1”, UCE bit = “0”)

17 INT1 O

C-bit Output Pin (when BCU bit = “1”, UCE bit = “1”)

18

P/SN

I

Parallel/Serial Select Pin

“L”: Serial control mode, “H”: Parallel control mode

FS96 O

96kHz Sampling Detect Pin in parallel control mode

This function is enabled when the input frequency of XTI is 24.576MHz.

“L”: fs=54kHz or less, “H”: fs=64kHz or more

19

I2C I

I2C Select Pin in serial control mode.

“L”: 4-wire Serial, “H”: I

2

C

20 INT0 O Interrupt #0 Pin

21 LRCK I/O Output Channel Clock Pin

22 SDTO O Audio Serial Data Output Pin

23 BICK I/O Audio Serial Data Clock Pin

24 DAUX I Auxiliary Audio Data Input Pin

Master Clock #2 Output Pin (when BCU bit = “0”)

25 MCKO2 O

Block Start Signal Output Pin (when BCU bit = “1”)

26 MCKO1 O Master Clock #1 Output Pin

OCKS0 I Output Clock Select #0 Pin in parallel control mode

CSN I Chip Select Pin in serial control mode, I2C pin = “L”

27

CAD0 I Chip Address #0 Pin in serial control mode, I2C pin = “H”

Note 1. Do not allow digital input pins except internal biased pins (RX1-6 pins) to float.

ASAHI KASEI [AK4113]

MS0349-J-02 2005/08

- 5 -

No. Pin Name I/O Function

OCKS1 I Output Clock Select #1 Pin in parallel control mode

CCLK I Control Data Clock Pin in serial control mode, I2C pin = “L”

28

SCL I Control Data Clock Pin in serial control mode, I2C pin = “H”

CM1 I Master Clock Operation Mode #1 Pin in parallel control mode

CDTI I Control Data Input Pin in serial control mode, I2C pin = “L”

29

SDA I/O

Control Data Pin in serial control mode, I2C pin = “H”

CM0 I Master Clock Operation Mode #0 Pin in parallel control mode

CDTO O Control Data Output Pin in serial control mode

30

CAD1 I Chip Address #1 Pin in serial control mode, I2C pin = “H”

Note 1. Do not allow digital input pins except internal biased pins (RX1-6 pins) to float.



Classification Pin Name

RX1, RX2/DIF0, RX3/DIF1, RX4/DIF2,

RX5, RX6/IPS

Analog Input

RX1, RX5

Digital Input

DAUX, XTI

DVSS

V/TX, XTO, INT0, INT1, MCKO1, MCKO2

I2C/FS96

Digital Output

CAD1/CDTO/CM0

4-wire mode (I2C pin

= “L”)

ASAHI KASEI [AK4113]

MS0349-J-02 2005/08

- 6 -

 AK4112B AK4113

Function AK4112B AK4113

Serial control mode 4ch 6ch

RX Input Channel

Parallel control mode 1ch 2ch

PLL Lock Range 22kHz to 108kHz 8kHz to 216kHz

Resistor value for R pin 18k ± 1% 15k ± 5%

PLL Lock Time ≤ 20ms

FAST bit =“0”: ≤ (15ms+384/fs)

FAST bit =“1”: ≤ (15ms+1/fs)

DTS-CD Bit Stream Detection Not available Available

DAT Start ID Detection Not available Available

Q-subcode Buffer for CD bit Stream Not available Available

fs Detection in serial control mode

≤ 54kHz

or

≥88.2kHz

8k / 11.025k / 16k / 22.05k / 24k/

32k / 44.1k / 48k / 64k / 88.2k /

96k / 176.4k / 192kHz

Serial µP Interface 4-wire 4-wire/I

2

C (max.400kHz)

Error Handling Pins AUTO, ERF, FS96 INT0, INT1

Master Clock Output Frequency 128fs/256fs/512fs 64fs/128fs/256fs/512fs

Channel Status Bit 32bit 40bit

MCKO2 Clock Source in serial control mode Depend on CM1-0 bits

Depend on CM1-0, XMCK and

BCU bits

Audio I/F at reset in serial control mode Master Mode Slave Mode

Package 28pin VSOP 30pin VSOP

ASAHI KASEI [AK4113]

MS0349-J-02 2005/08

- 7 -

2.

:

1) AK4112B AK4113 .

2) ( ) AK4112B

3.

AK4112B AK4113

6

5

4

3

2

1

DVDD

DVSS

V/TX

TVDD

XTI

XTO

PDN 7

R

8

Top

View

10

9

A

VDD

A

VSS

RX1

11

RX2/DIF0 12

13

14

RX3/DIF1

RX4/DIF2

CM0/CDTO/CAD1

CM1/CDTI/SDA

OCKS1/CCLK/SCL

OCKS0/CSN/CAD0

MCKO1

MCKO2

DAUX

BICK

SDTO

LRCK

INT0 (ERF)

FS96/I2C (FS96)

25

26

27

28

29

30

24

23

21

22

20

19

18

17

P/SN

INT1 (AUTO)

15

(None) RX5

16

IPS/RX6 (None)

A

K4112B

A

K4113

ASAHI KASEI [AK4113]

MS0349-J-02 2005/08

- 8 -

(AVSS, DVSS=0V; Note 2)

Parameter Symbol Min max Units

Power Supplies: Analog

Digital

Input Buffer

|AVSS-DVSS| (Note 3)

AVDD

DVDD

TVDD

∆GND

-0.3

4.6

6.0

0.3

V

Input Current (Any pins except supplies) IIN -

±10

mA

Input Voltage VIN -0.3 TVDD+0.3 V

Ambient Temperature (Power applied) Ta -40 85

°C

Storage Temperature Tstg -65 150

°C

Note 2.

Note 3. AVSS, DVSS

:

(AVSS, DVSS=0V; Note 2)

Parameter Symbol min typ max Units

Power Supplies: Analog

Digital

Input Buffer

Difference

AVDD

DVDD

TVDD

AVDD - DVDD

2.7

DVDD

-0.3

3.3

0

3.6

5.5

0.3

V

Note 2.

S/PDIF

(Ta=25°C; AVDD, DVDD=2.7~3.6V;TVDD=2.7~5.5V)

Parameter Symbol min typ max Units

Input Resistance Zin 10

kΩ

Input Voltage VTH 350 mVpp

Input Hysteresis VHY - 185 mV

Input Sample Frequency fs 8 - 216 kHz

ASAHI KASEI [AK4113]

MS0349-J-02 2005/08

- 9 -

DC

(Ta=25°C; AVDD, DVDD=2.7~3.6V;TVDD=2.7~5.5V; unless otherwise specified)

Parameter Symbol min typ max Units

Power Supply Current

Normal operation: PDN pin = “H” (Note 4)

Power down: PDN pin = “L” (Note 5)

26

10

42

100

mA

µA

High-Level Input Voltage

Low-Level Input Voltage

VIH

VIL

70%DVDD

DVSS - 0.3

-

TVDD

30%DVDD

V

High-Level Output Voltage

(Except TX pin: Iout=-400µA)

Low-Level Output Voltage

(Except TX and SDA pin: Iout=400µA)

( SDA pin: Iout= 3mA)

VOH

VOL

DVDD-0.4

-

0.4

V

TX Output Level (Note 6) VTXO 0.4 0.5 0.6 V

Input Leakage Current (Except RX1-6, XTI pins) Iin - -

± 10 µA

Note 4. AVDD, DVDD=3.3V, TVDD=5.0V, C

L

=20pF, fs=216kHz, X'tal=24.576MHz, Clock Operation Mode 2, OCKS1

bit = “1”, OCKS0 bit = “1”, Master mode, TX pin Figure 19 AVDD=5mA (typ),

DVDD=21mA (typ), TVDD=0.1µA (typ)

Note 5. RX DVDD DVSS

Note 6. Figure 19

(Ta=25°C; AVDD, DVDD=2.7~3.6V, TVDD=2.7~5.5V; C

L

=20pF)

Parameter Symbol min typ max Units

Master Clock Timing

Crystal Resonator Frequency fXTAL 11.2896 24.576 MHz

External Clock Frequency

Duty

fECLK

dECLK

11.2896

40

50

24.576

60

MHz

%

MCKO1 Output Frequency

Duty

fMCK1

dMCK1

1.024

40

50

27.648

60

MHz

%

MCKO2 Output Frequency

Duty

fMCK2

dMCK2

0.512

40

50

27.648

60

MHz

%

PLL Clock Recover Frequency (RX1-6) fpll 8 - 216 kHz

LRCK Frequency

Duty Cycle

fs

dLCK

8

45

216

55

kHz

%

Audio Interface Timing

Slave Mode

BICK Period

BICK Pulse Width Low

Pulse Width High

LRCK Edge to BICK “↑” (Note 7)

BICK “↑” to LRCK Edge (Note 7)

LRCK to SDTO (MSB)

BICK “↓” to SDTO

DAUX Hold Time

DAUX Setup Time

tBCK

tBCKL

tBCKH

tLRB

tBLR

tLRM

tBSD

tDXH

tDXS

72

27

15

20

ns

Master Mode

BICK Frequency

BICK Duty

BICK “↓” to LRCK

BICK “↓” to SDTO

DAUX Hold Time

DAUX Setup Time

fBCK

dBCK

tMBLR

tBSD

tDXH

tDXS

-15

15

64fs

50

15

Hz

%

ns

Note 7. LRCK BICK

ASAHI KASEI [AK4113]

MS0349-J-02 2005/08

- 10 -

(Ta=25°C; AVDD, DVDD=2.7~3.6V, TVDD=2.7~5.5V; C

L

=20pF)

Parameter Symbol min typ max Units

Control Interface Timing (4-wire serial mode)

CCLK Period

CCLK Pulse Width Low

Pulse Width High

CDTI Setup Time

CDTI Hold Time

CSN “H” Time

CSN “↓” to CCLK “↑”

CCLK “↑” to CSN “↑”

CDTO Delay

CSN “↑” to CDTO Hi-Z

tCCK

tCCKL

tCCKH

tCDS

tCDH

tCSW

tCSS

tCSH

tDCD

tCCZ

200

80

50

150

50

45

70

ns

Control Interface Timing (I

2

C Bus mode):

SCL Clock Frequency

Bus Free Time Between Transmissions

Start Condition Hold Time (prior to first clock pulse)

Clock Low Time

Clock High Time

Setup Time for Repeated Start Condition

SDA Hold Time from SCL Falling (Note 8)

SDA Setup Time from SCL Rising

Rise Time of Both SDA and SCL Lines

Fall Time of Both SDA and SCL Lines

Setup Time for Stop Condition

Capacitive load on bus

Pulse Width of Spike Noise Suppressed by Input Filter

fSCL

tBUF

tHD:STA

tLOW

tHIGH

tSU:STA

tHD:DAT

tSU:DAT

tR

tF

tSU:STO

Cb

tSP

-

1.3

0.6

1.3

0.6

0

0.1

-

0.6

-

0

400

-

0.3

-

400

50

kHz

µs

pF

ns

Reset Timing

PDN Pulse Width

tPW

150

ns

Note 8. 300ns (SCL )

Note 9. I

2

C Philips Semiconductors

ASAHI KASEI [AK4113]

MS0349-J-02 2005/08

- 11 -



1/fECLK

tECLKL

VIH

tECLKH

XTI

VIL

dECLK = tECLKH x fECLK x 100

= tECLKL x fECLK x 100

1/fMCK1

50%DVDD MCKO1

tMCKL1tMCKH1

dMCK1 = tMCKH1 x fMCK1 x 100

= tMCKL1 x fMCK1 x 100

1/fMCK2

50%DVDD

MCKO2

tMCKL2tMCKH2

dMCK2 = tMCKH2 x fMCK2 x 100

= tMCKL2 x fMCK2 x 100

1/fs

LRCK

VIH

VIL

tLRLtLRH

dLCK = tLRH x fs x 100

= tLRL x fs x 100

Figure 3.

tLRB

LRCK

BICK

SDTO

tBSD

tBLR tBCKL tBCKH

tLRM

50%DVDD

DAUX

tDXS tDXH

VIH

VIL

VIH

VIL

VIH

VIL

tBCK

Figure 4. (Slave mode)

ASAHI KASEI [AK4113]

MS0349-J-02 2005/08

- 12 -

LRCK

BICK

SDTO

tBSD

tMBLR

50%DVDD

DAUX

tDXHtDXS

VIH

VIL

Figure 5. (Master mode)

tCCKL

CSN

CCLK

tCDS

CDTI

tCDH

tCSS

C0 A4

tCCKH

CDTO

Hi-Z

R/W

C1

VIH

VIL

VIH

VIL

VIH

VIL

tCCK

Figure 6. WRITE/READ (4-wire serial control mode)

ASAHI KASEI [AK4113]

MS0349-J-02 2005/08

- 13 -

tCSW

CSN

CCLK

CDTI D2 D0

tCSH

CDTO

Hi-Z

D1D3

VIH

VIL

VIH

VIL

VIH

VIL

Figure 7. WRITE (4-wire serial mode)

CSN

CCLK

tDCD

CDTO

D7 D6

CDTI

A1 A0

D5

Hi-Z

50%DVDD

VIH

VIL

VIH

VIL

VIH

VIL

Figure 8. READ 1 (4-wire serial mode)

CSN

CCLK

tCCZ

CDTO

D2 D1

CDTI

D0

D3

tCSW

tCSH

50%DVDD

VIH

VIL

VIH

VIL

VIH

VIL

Figure 9. READ 2 (4-wire serial mode)

ASAHI KASEI [AK4113]

MS0349-J-02 2005/08

- 14 -

tHIGH

SCL

SDA

VIH

tLOW

tBUF

tHD:STA

tR

tF

tHD:DAT tSU:DAT tSU:STA

Stop Start Start Stop

tSU:STO

VIL

VIH

VIL

tSP

Figure 10. I

2

C

tPW

PDN

VIL

Figure 11.

ASAHI KASEI [AK4113]

MS0349-J-02 2005/08

- 15 -

 Non-PCM/DTS-CD

AK4113 Non-PCM Dolby “Dolby Digital Data Stream in IEC60958

Interface” 32 Mode Non-PCM NPCM bit “1”

96 sync code 0x0000, 0x0000, 0x0000, 0x0000, 0xF872 and 0x4E1F

NPCM bit “1” 4096 4096 sync code

NPCM bit = “0” sync code NPCM bit “0”

sync code 2 (Pc: burst information, Pd: length code; Table 17,

Table 18 ) DTS-CD DTSCD bit

“1” 4096 sync code DTSCD bit = “0” sync

code DTSCD bit “0” NPCM bit DTSCD bit OR AUTO bit

AK4113 DTS-CD 14bit Sync Word, 16bit Sync Word

DTS14 bit, DTS16 bit ON/OFF

AUTO bit AUDION bit

OR INT1 pin

DTS-CD 14bit Sync Word, 16bit Sync Word

 216kHz

PLL 8kHz 216kHz PLL

(fs) FAST bit Figure 12 FAST bit

FAST bit = “1” XTL1-0 bits

(8kHz, 11.025kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz, 64kHz, 88.2kHz,

96kHz, 176.4kHz, 192kHz) 24.576MHz

64kHz FS96 pin “H” 54kHz “L”

FAST bit PLL Lock Time

0

≤ (15 ms + 384/fs)

Default

1

≤ (15 ms + 1/fs)

Figure 12. PLL Lock Time (fs: Sampling Frequency)

ASAHI KASEI [AK4113]

MS0349-J-02 2005/08

- 16 -



RX DAUX CM0 CM1

CM0 CM1 Mode 2 PLL Unlock

X'tal Mode 3 X’tal

RX Mode 2, 3 PLL X'tal

Mode CM1 CM0 UNLOCK PLL X'tal Clock source SDTO

0 0 0 - ON ON (Note) PLL RX

1 0 1 - OFF ON X'tal DAUX

0 ON ON PLL RX

2 1 0

1 ON ON X'tal DAUX

3 1 1 - ON ON X'tal DAUX

Default

ON: (Power-up), OFF: (Power-Down)

Note: X’tal (XTL1-0 bit = “11”) OFF

Table 1.



AK4113 2 (MCKO1 pin and MCKO2 pin) MCKO2 pin XMCK

bit 2

1) XMCK bit = “0”, BCU bit = “0”

AK4112B, AK4114 PLL

X'tal (Table 2) (MCKO1 pin, MCKO2 pin)

X’tal fs OCKS1-0 96kHz 512fs 192kHz 256fs,512fs

No. OCKS1 OCKS0 MCKO1 pin MCKO2 pin X’tal fs (max)

0 0 0 256fs 256fs 256fs 108 kHz

1 0 1 256fs 128fs 256fs 108 kHz

2 1 0 512fs 256fs 512fs 54 kHz

3 1 1 128fs 64fs 128fs 216 kHz

Default

Table 2.

2) XMCK bit = “1”, BCU bit = “0”

MCKO2 pin CM1-0 bit, OCKS1-0 bit XTI pin

DIV bit MCKO1 pin CM1-0 bit, OCKS1-0 bit

XMCK bit DIV bit MCKO2 Clock Source MCKO2 Frequency

1 0

X’tal x 1

1 1 X’tal x 1/2

Table 3. MCKO2 pin

ASAHI KASEI [AK4113]

MS0349-J-02 2005/08

- 17 -



AK4113 XTI pin

1) X’tal

XTI

XTO

AK4113

Figure 13. X’tal

Note: (typ.10-40pF)

2)

XTI

XTO

AK4113

External Clock

Figure 14.

3) XTI/XTO

XTI

XTO

AK4113

Figure 15. OFF

ASAHI KASEI [AK4113]

MS0349-J-02 2005/08

- 18 -



AK4113 2

XTL1-0 bit X’tal FS3-0 bits

X’tal XTL1-0 bits = “11”

FS3-0 bits

XTL1-0 bit = “10”

XTL1 bit XTL0 bit X’tal Frequency

0 0 11.2896MHz

0 1 12.288MHz

1 0 24.576MHz

1 1

Default

Table 4.

XTL1-0 bit = “11”

Register output

fs

Consumer

mode

(Note 11)

Professional mode

(Note 12)

FS3 FS2 FS1 FS0

Clock comparison

(Note 10)

Byte3

Bit3,2,1,0

Byte0

Bit7,6

Byte4

Bit6,5,4,3

0 0

44.1kHz

44.1kHz ± 3%

0 0 0 0 0 1

0 0 0 0

0 0 0 1 Reserved - 0 0 0 1 (Others)

0 0

1 0

48kHz

48kHz ± 3%

0 0 1 0 1 0

0 0 0 0

0 0

1 1

32kHz

32kHz ± 3%

0 0 1 1 1 1

0 0 0 0

0 1

0 0

22.05kHz

22.05kHz ± 3%

0 1 0 0 0 0

1 0 0 1

0 1 0 1 11.025kHz

11.025kHz ± 3%

0 1

1 0

24kHz

24kHz ± 3%

0 1 1 0 0 0

0 0 0 1

0 1 1 1 16kHz

16kHz ± 3%

1 0

0 0

88.2kHz

88.2kHz ± 3%

1 0 0 0 0 0

1 0 1 0

1 0 0 1 8kHz

8kHz ± 3%

1 0

96kHz

96kHz ± 3%

1 0 1 0 0 0

0 0 1 0

1 0 1 1 64kHz

64kHz ± 3%

1 1

0 0

176.4kHz

176.4kHz ± 3%

1 1 0 0 0 0

1 0 1 1

1 1

1 0

192kHz

192kHz ± 3%

1 1 1 0 0 0

0 0 1 1

Note 10. ±3%

8kHz ∼ 216kHz FS3-0

bits = “0001”, “1101”

Note 11. Byte3 Bit3-0 FS3-0 bits

Note 12. Table 5 FS3-0 bit=“0001”

Table 5.

ASAHI KASEI [AK4113]

MS0349-J-02 2005/08

- 19 -

PEM bit

(CS12 bit = “0” ) 1 CS12 bit =

“1” 2

PEM bit Pre-emphasis

Byte 0

Bits 3-5

0 OFF

≠ 0X100

1 ON 0X100

Table 6.

PEM bit Pre-emphasis

Byte 0

Bits 2-4

0 OFF

≠110

1 ON 110

Table 7.



IIR 3 (32kHz, 44.1kHz, 48kHz) (50/15µs )

DEAU bit = “1” FS3-0 bits

DEAU bit = “0” DEM1-0 bits

OFF

PEM bit = “0”

PEM bit FS3 bit FS2 bit FS1 bit FS0 bit Mode

1 0 0 0 0 44.1kHz

1 0 0 1 0 48kHz

1 0 0 1 1 32kHz

1 (Others) OFF

0 x x x x OFF

Table 8. (DEAU bit = “1”: Default)

PEM bit DEM1 bit DEM0 bit Mode

1 0 0 44.1kHz

1 0 1 OFF Default

1 1 0 48kHz

1 1 1 32kHz

0 x x OFF

Table 9. (DEAU bit = “0”)

ASAHI KASEI [AK4113]

MS0349-J-02 2005/08

- 20 -



AK4113 PDN pin PWN bit RSTN bit

PDN pin

PDN pin “L”

PDN pin:

“L”

RSTN bit ( 00H D0):

“0” PWN RSTN

“0” SDTO pin “L” PWN RSTN

PWN bit ( 00H D1):

“0” PLL

X’tal

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AKM AK4113VF 仕様

AKM AK4113VF 仕様

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