AKM AK4103AVF 仕様

[AK4103A]

MS0251-J-01 2009/01

- 1 -

AK4103A 192kHz (DIT) AK4103A AES3,

IEC60958, S/PDIF, EIAJ CP1201 AK4103A

8

 192kHz



AES3, IEC60958, S/PDIF, EIAJ CP1201 &



CRCC ,



RS422



& 16



&



: 128fs, 256fs, 384fs, 512fs



: / /I

2

S



4



( )



: 4.75 ∼ 5.25V



TTL I/F



: 24 VSOP



Ta: -40 ∼ 85 °C

192kHz 24-Bit DIT

AK4103A

[AK4103A]

MS0251-J-01 2009/01

- 2 -

■

Host Serial

Interface

Audio Serial

Interface

BICK

LRCK

SDTI

TXP

MUX

CRCC Generator

Prescaler

RS422 Line Driver

Biphase

Encoder

DIF2

DIF1

DIF0

CKS1

CKS0

MCLK

BLS

TRANS

VSS

VDD

TXN

C1

U1

V1

FS0

FS1

FS2

FS3

Register

CSN

CCL

K

CDTI

CDTO

ANS

PDN

[AK4103A]

MS0251-J-01 2009/01

- 3 -

■

AK4103AVF -40 ∼ +85°C 24pin VSOP (0.65mm pitch)

AKD4103A Evaluation Board for AK4103A

■

6

5

4

3

2

1V1

TRANS

MCLK

PDN

SDTI

BICK

LRCK 7

FS0/CSN 8

U1

DIF2

DIF1

DIF0

TXP

TXN

VSS

VDD

Top

View

10

9FS1/CDTI

FS2/CCLK

FS3/CDTO 11

C1 12

CKS1

CKS0

BLS

A

NS

19

20

21

22

23

24

18

17

15

16

14

13

■ AK4103

Function AK4103

AK4103A

Ambient Temperature

-10 ~ 70°C -40 ~ 85°C

CRCC generation by FS3-0 pins. Synchronous mode X

O

CRCC generation by FS3-0 bits. Asynchronous mode X

O

O: CRCC

X: CRCC

[AK4103A]

MS0251-J-01 2009/01

- 4 -

No.

I/O

1 V1 I

2 TRANS I

( )

0:

1: ( )

3 PDN I

& ( )

“L” TXP/N

“L”

4 MCLK I

5 SDTI I

6 BICK I/O

SDTI pin DIF2-0

7 LRCK I/O

L/R DIF2-0

FS0 I

0 ( ) ( )

CSN I

( )

8

AKMODE I

AK4112B ( )

( )

0: AKM , 1: AK4112B

FS1 I

1 ( ) ( )

9

CDTI I

( )

FS2 I

2 ( ) ( )

10

CCLK I

( )

FS3 I

3 ( ) ( )

11

CDTO O

( )

12 C1 I

13 ANS I

( )

0: (Asynchronous) , 1: (Synchronous)

14 BLS I/O

( )

4 “H”

PDN pin = “L” BLS pin “H”

15 CKS0 I

0 ( )

16 CKS1 I

1 ( )

17 VDD -

, 4.75V∼5.25V

18 VSS -

, 0V

19 TXN O

20 TXP O

21 DIF0 I

0 ( )

22 DIF1 I

1 ( )

23 DIF2 I

2 ( )

24 U1 I

( )

Note 1. 43kΩ (typ)

Note 2.

[AK4103A]

MS0251-J-01 2009/01

- 5 -

(VSS=0V; Note 3)

Parameter Symbol min max Units

Power Supply VDD -0.3 6.0 V

Input Current (All pins except supply pins) IIN -

±10

mA

Input Voltage VIND -0.3 VDD+0.3 V

Ambient Operating Temperature Ta -40 85

°C

Storage Temperature Tstg -65 150

°C

Note 3.

:

(VSS=0V; Note 3)

Parameter Symbol min typ max Units

Power Supply VDD 4.75 5.0 5.25 V

:

DC

(Ta=25°C; VDD=4.75~5.25V)

Parameter Symbol min typ max Units

Power Supply Current (fs=108kHz, Note 4) IDD 6 15 mA

High-Level Input Voltage

Low-Level Input Voltage

VIH

VIL

2.4

-

0.8

V

High-Level Output Voltage

(Except TXP/N pins: Iout=-400µA)

(TXP/N pins: Iout= -8mA)

Low-Level Output Voltage

(Except TXP/N pins: Iout= 400µA)

(TXP/N pins: Iout= 8mA)

VOH

VOL

VDD-1.0

VDD-0.8

-

0.4

0.6

V

Input Leakage Current Iin - - ±10 μA

Note 4. 3mA(typ)@fs=48kHz, 9mA(typ)@fs=192kHz.

20mA(typ)

PDN pin = “L”, TRANS pin = “H” VSS

350μA(typ)

[AK4103A]

MS0251-J-01 2009/01

- 6 -

(Ta=25°C; VDD=4.75~5.25V; C

L

=20pF)

Parameter Symbol min typ max Units

Master Clock Timing

Frequency

Duty Cycle

fCLK

dCLK

3.584

40

27.648

60

MHz

%

LRCK Timing

Frequency

Duty Cycle at Slave Mode

Duty Cycle at Master Mode

fs

dLCK

28

45

50

192

55

kHz

%

Audio Interface Timing

Slave Mode

BICK Period

BICK Pulse Width Low

Pulse Width High

LRCK Edge to BICK “↑” (

Note 5)

BICK “↑” to LRCK Edge (

Note 5)

SDTI Hold Time

SDTI Setup Time

tBCK

tBCKL

tBCKH

tLRB

tBLR

tSDH

tSDS

36

15

8

ns

Master Mode

BICK Frequency

BICK Duty

BICK “↓” to LRCK

SDTI Hold Time

SDTI Setup Time

fBCK

dBCK

tMBLR

tSDH

tSDS

-20

20

64fs

50

20

Hz

%

ns

Control Interface Timing

CCLK Period

CCLK Pulse Width Low

Pulse Width High

CDTI Setup Time

CDTI Hold Time

CSN “H” Time

CSN “↓” to CCLK “↑”

CCLK “↑” to CSN “↑”

CDTO Delay

CSN “↑” to CDTO Hi-Z (

Note 6)

tCCK

tCCKL

tCCKH

tCDS

tCDH

tCSW

tCSS

tCSH

tDCD

tCCZ

200

80

50

520

50

45

70

ns

Power-down & Reset Timing

PDN Pulse Width

tPDW

150

ns

Note 5. LRCK BICK

Note 6. CDTO pin

[AK4103A]

MS0251-J-01 2009/01

- 7 -

■

1/fCLK

tCLKL

VIH

tCLKH

MCLK

VIL

dCLK = tCLKH x fCLK x 100

= tCLKL x fCLK x 100

VIH

LRCK

VIL

1/fs

tBCK

tBCKL

VIH

tBCKH

BICK

VIL

tLRB

LRCK

VIH

BICK

VIL

tSDS

VIH

SDTI

VIL

tSDH

VIH

VIL

tBLR

( )

LRCK

BICK

tMBLR

50%VDD

SDTI

tSDHtSDS

VIH

VIL

( )

[AK4103A]

MS0251-J-01 2009/01

- 8 -

tCCKL

CSN

CCLK

tCDS

CDTI

tCDH

tCSS

C0 *

tCCKH

CDTO

Hi-Z (with pull-down resistor)

*

C1

VIH

VIL

VIH

VIL

VIH

VIL

WRITE/READ

tCSW

CSN

CCLK

CDTI D2 D0

tCSH

CDTO

D1D3

VIH

VIL

VIH

VIL

VIH

VIL

Hi-Z

(with pull-down resistor)

WRITE

CSN

CCLK

tDCD

CDTO

CDTI

A1 A0

Hi-Z

(with pull-down

resistor)

50%VDD

VIH

VIL

VIH

VIL

VIH

VIL

D7 D6 D5

[AK4103A]

MS0251-J-01 2009/01

- 9 -

CSN

CCLK

tCCZ

CDTO

D2 D1

CDTI

D0

D3

tCSW

tCSH

50%VDD

VIH

VIL

VIH

VIL

VIH

VIL

tPDW

RESETN

VIL

&

[AK4103A]

MS0251-J-01 2009/01

- 10 -

■

AK4103A AES3, IEC60958, S/PDIF, EIAJ CP1201

CMOS

(asynchronous) (synchronous) 2 “ / ”

■

PDN pin 8 BICK MCLK

LRCK

■ MCLK LRCK

MCLK LRCK ( )

( DSP ) BICK LRCK

MCLK LRCK (128fs x 3)

MCLK

CKS1 CKS0 MCLK Fs

0 0 128fs 28k-192kHz

0 1 256fs 28k-108kHz

1 0 384fs 28k-54kHz

1 1 512fs 28k-54kHz

Table 1. MCLK

■ (Asynchronous) (Synchronous)

1. (Asynchronous) ( )

ANS pin “L” 16 24

4

RS422

CRCC AES3

[AK4103A]

MS0251-J-01 2009/01

- 11 -

2. (Synchronous) ( )

16 24

RS422

2-1. ( )

ANS pin = TRANS pin = “H” ( )

(C) (U) (V)

(B)

C,U,V CRCC

C bit FS0/CSN pin AKMODE pin

“H” AK4112B “L” AKM

TRANS pin = “H”, ANS pin = “L”

Pin Modes

ANS TRANS Synchronous/Asynchronous Audio Routing

Source for C, U and V bits

L L Asynchronous mode Normal mode

C Pin ORed Control Register

U Pin ORed Control Register

V Pin ORed Control Register

L H (Test mode)

H L Normal mode

H H

Synchronous mode

Audio routing mode

C,U and V pin

Table 2.

BLS

C (or U,V)

C(L0) C(R0) C(L1) C(R31)C(L31) C(L32)

C(R191)

SDTI

LRCK

(I

2

S)

L0 R0 L31 R31R191 L1 L32

LRCK

(except I

2

S)

Figure 1. (AKMODE pin = “0”)

[AK4103A]

MS0251-J-01 2009/01

- 12 -

BLS

C (or U,V)

LRCK

C(L0) C(R0) C(L1) C(R31)C(L31) C(L32)

C(R191)

SDTI

(except I

2

S)

L191 R191 L0 R30

R31

L31

SDTI

(I

2

S)

L191 R191 L30

L31

R30

L0

R190

R0

Figure 2. (AKMODE pin = “1”)

■

(TRANS pin = “L”) 0

2 2BICK “H” 32 “H”

( ) (ANS pin = TRANS pin = “H”)

I

2

S Lch BICK

LRCK BICK Lch

1

Figure 3

BICK

LRCK

(except I

2

S)

(n-1)th channel 1 nth channel 1

LRCK

(I

2

S)

(n-1)th channel 1 nth channel 1

(1)

Figure 3.

“(1)” “nth channel 1” 1

[AK4103A]

MS0251-J-01 2009/01

- 13 -

■ C, U, V

(TRANS pin = “L”) C, U, V bit

( ) V bit “0”

Figure 4 Figure 5

( ) (ANS pin=TRANS pin= “H”) CUV bit

Mode 5 7 DIF mode CUV bit LRCK

BICK Mode 5 7(I

2

S) CUV bit

LRCK 2 BICK

Figure 6 Figure 7

C,U,V

BICK

LRCK

Channel1

Channel 2

Channel 1

C,U,

V

Previous Channel 2

C, U, V

Figure 4. Normal, DIF modes 0/1/2/3/4/6

C,U,V

BICK

LRCK

Channel 1

Channel 2

Channel 1

C, U,

V

Previous Channel 2

C, U, V

Figure 5. Normal, DIF modes 5 and 7 (I

2

S)

C,U,V

BICK

LRCK

Channel 1

C, U,

V

Channel 1

Channel 2

C, U,

V

Figure 6. Audio routing, DIF modes 0/1/2/3/4/6

[AK4103A]

MS0251-J-01 2009/01

- 14 -

C,U,V

BICK

LRCK

Channel 1

C, U,

V

Channel 1

Channel 2

C, U,

V

Figure 7. Audio routing, DIF modes 5 and 7 (I

2

S)

■

(BICK)

(LRCK) (SDTI) 3 SDTI BICK

LRCK L R DIF2-0 pin

DIF2-0 pin OR

16 24

I

2

S AK4103A

Mode DIF2 DIF1 DIF0 SDTI Master / Slave LRCK BICK

0 0 0 0 16bit, Right justified Slave H/L (I) 32fs-128fs (I)

1 0 0 1 18bit, Right justified Slave H/L (I) 36fs-128fs (I)

2 0 1 0 20bit, Right justified Slave H/L (I) 40fs-128fs (I)

3 0 1 1 24bit, Right justified Slave H/L (I) 48fs-128fs (I)

4 1 0 0 24bit, Left justified Slave H/L (I) 48fs-128fs (I)

5 1 0 1 24bit, I

2

S Slave L/H (I) 50fs-128fs (I)

6 1 1 0 24bit, Left justified Master H/L (O) 64fs (O)

7 1 1 1 24bit, I

2

S Master L/H (O) 64fs (O)

Table 3. [NOTE: (I): Input, (O): Output]

LRCK(i)

BICK(i)

SDTI(i)

012 31 0 1

15:MSB, 0:LSB

Lch Data

Rch Data

15 1716 1531 0 1 2 1716

0101

30

15 141415

30

Figure 8. Mode 0

[AK4103A]

MS0251-J-01 2009/01

- 15 -

LRCK(i)

BICK(i)

SDTI(i)

0 1 2 31 0 1

17:MSB, 0:LSB

Lch Data

Rch Data

13 15 14 1331 0 1 2 15 14

01 0 1

30

17 16 16 17

30

Figure 9. Mode 1

LRCK(i)

BICK(i)

SDTI(i)

0 1 2 31 0 1

19:MSB, 0:LSB

Lch Data

Rch Data

11 13 12 1131 0 1 2 13 12

01 0 1

30

19 18 18 19

30

Figure 10. Mode 2

LRCK(i)

BICK(i)

SDTI(i)

01 8 31 0 1

23:MSB, 0:LSB

Lch Data

Rch Data

91110 931 0 1 8 1110

0101

30

21 202021

30

2223 2223

Figure 11. Mode 3

[AK4103A]

MS0251-J-01 2009/01

- 16 -

LRCK

BICK

SDTI(i)

012 31 0 1

23:MSB, 0:LSB

Lch Data

Rch Data

21 2322 2131 0 1 2 2322

23 222

30

1 001

30

212223 21 2 23 22

Figure 12. Mode 4/6

Mode 4: LRCK, BICK: Input

Mode 6: LRCK, BICK: Output

LRCK

BICK

SDTI(i)

012 31 0 1

23:MSB, 0:LSB

Lch Data

Rch Data

233231 0 1 233

23 22

24

1 0

24

32 23

22

2 01212223

22

Figure 13. Mode 5/7

Mode 5: LRCK, BICK: Input

Mode 7: LRCK, BICK: Output

[AK4103A]

MS0251-J-01 2009/01

- 17 -

■

3 3-0 FS3-0 pin

0 7-6 4 6-

3 FS3-0 pin

FS[3:0]

Sampling

Frequency

Byte 3

Bits 3-0

0000 44.1kHz 0000

0001 Not Indicated 0001

0010 48kHz 0010

0011 32kHz 0011

0100 22.05kHz 0100

0101 Reserved 0101

0110 24kHz 0110

0111 Reserved 0111

1000 88.2kHz 1000

1001 Reserved 1001

1010 96kHz 1010

1011 Reserved 1011

1100 176.4kHz 1100

1101 Reserved 1101

1110 192kHz 1110

1111 Reserved 1111

Table 4. ( )

FS[3:0] Fs

Byte 0

Bits 7-6

Byte 4

Bits 6-3

0000 Not Defined 00 0000

0001 44.1kHz 01 0000

0010 48kHz 10 0000

0011 32kHz 11 0000

0100 Not Defined 00 0000

0101 Not Defined 00 0000

0110 Not Defined 00 0000

0111 Not Defined 00 0000

1000 For vectoring 00 1000

1001 22.05kHz 00 1001

1010 88.2kHz 00 1010

1011 176.4kHz 00 1011

1100 192kHz 00 0011

1101 24kHz 00 0001

1110 96kHz 00 0010

1111 Not Defined 00 1111

Table 5. ( )

[AK4103A]

MS0251-J-01 2009/01

- 18 -

■

TX

Figure 14 192

2 32

2

0 1

Figure 15 16 8

Frame 191 Frame 0 Frame 1

Sub-frame Sub-frame

M

Channel 1 W Channel 2 B Channel 1 W Channel 2 M Channel 1 W Channel 2

Figure 14.

0 1 1 0 0 0 1 0

Figure 15.

Figure 16 0-3

3 (B) 0 1

1 (M) 0 1 2

(W) 2

Table 6 4-27 24

2 27 MSB 16 4-11

0 28 “H”

29 192

0 191 30

192 0

191 31 4-31

Sync P

C

UV

L M

S Audio sample S

B B

0 3 4 27 28 29 30 31

Figure 16.

(fs) 64

L A 1 R B

2 1

Preamble Preceding state = 0 Preceding state = 1

B 11101000 00010111

M 11100010 00011101

W 11100100 00011011

Table 6.

[AK4103A]

MS0251-J-01 2009/01

- 19 -

■

AK4103A RS422 AES3 110Ω

±20% 110Ω 2∼7Vpp

RS422 56Ω

(S/PDIF) 75Ω ±20% 0.5Vpp±20% 330Ω

100Ω

TXP

TXN

56 0.1u

XLR Connector

Transformer

Figure 17.

TXP

TXN

330 0.1u

RCA Phono

Connector

Transformer

100

Figure 18.

[AK4103A]

MS0251-J-01 2009/01

- 20 -

■

4 4 CSN , CCLK, CDTI, CDTO

pins 18

AK4103A

Figure 19

C1-0 bits

AK4103A C1-0 bits “11” R/W bit “0” “1”

A7-0 bits

CDTI pin D7-0 bits

CDTO pin D7-0 bits

CSN pin = “L”

CCLK

CCLK CDTO CCLK

CCLK 5MHz

CDTI

CCLK

CSN

C1

0 1 2 3 4 5 6 7

16 17 18 19 20 21 22 23

D4 D5 D6D7** * * * C0 R/W D0D1 D2 D3

CDTO

Hi-Z (with pull-down resistor)

WRITE

CDTI

C1 D4 D5 D6D7** * * * C0 R/W D0D1 D2 D3

CDTO

Hi-Z (with pull-down resistor)

READ

D4 D5 D6D7 D0D1 D2 D3

Hi-Z

A7

8 9 101112131415

A1A2A3A4A5A6 A0

A7 A1A2A3A4A5A6 A0

“L”

C1-C0: Chip Address (Fixed to “11”)

R/W: READ/WRITE (0:READ, 1:WRITE)

*: Don’t care

A7-A0: Register Address

D7-D0: Control Data

Figure 19.

CSN

AK4103A

CCLK

CDTI

CDTO

CSN

AK4103A

CCLK

CDTI

CDTO

μ

P

CSN1

CCLK

CDTI

CDTO

CSN2

Figure 20. Typical connection with μP

Note: CDTO p in

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AKM AK4103AVF 仕様

AKM AK4103AVF 仕様

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