[AK4127]
MS0593-J-02 2010/05
- 1 -
AK4127 (SRC) 8kHz ∼ 216kHz
8kHz ∼ 216kHz
PLL
/DVD
1. SRC
• Asynchronous Sample Rate Converter
• Input Sample Rate Range (fsi): 8kHz ∼ 216kHz
• Output Sample Rate Range (fso): 8kHz ∼ 216kHz
• Input to Output Sample Rate Ratio: 1/6 to 6
• THD+N: −130dB
• Dynamic Range: 140dB (A-weighted)
• I/F format: MSB justified, LSB justified, I
2
S compatible and TDM
• PLL for Internal Operation Clock
• Clock for Master mode: 128/192/256/384/512/768fsi, 128//256/384/512/768fso
• SRC Bypass mode (Master/Slave)
• Soft Mute Function
2. Power Supply
• AVDD, DVDD: 3.0 ∼ 3.6V (typ. 3.3V)
3. Ta = −40
∼ 85°C
4. Package: 30pin VSOP
5. AK4124/25 Pin-compatible
PLL
PDN
SMUTE
OLRCK
OBICK
SDTO
OMCLK
Serial
Audio
I/F
SRC
Serial
Audio
I/F
ILRCK
SDTI
IBICK
PLL1
PLL2
IDIF2
IDIF1 IDIF0 ODIF1 ODIF0
OBIT1
OBIT0
UNLOCK IMCLK
AVDD AVSS DVDD DVSS
CMODE2
CMODE1 CMODE0
PLL0
DITHER
192kHz / 24Bit High Performance Asynchronous SRC
AK4127
[AK4127]
MS0593-J-02 2010/05
- 2 -
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AK4125 ...................................................................................................................................................... 4
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SRC ............................................................................................................................................................................. 7
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DC ............................................................................................................................................................................... 9
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TDM ......................................................................................................................... 18
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PLL .......................................................................................................................................... 22
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Material & Lead finish............................................................................................................................................. 27
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[AK4127]
MS0593-J-02 2010/05
- 3 -
■
AK4127VF −40 ∼ +85°C 30pin VSOP (0.65mm pitch)
AKD4127 AK4127
■
PDN
SMUTE
ILRCK
IBICK
FILT
AVSS
DITHER
PLL2
IDIF0
IDIF1
IDIF2
PLL0
PLL1
SDTI
Top View
8
7
6
5
4
3
2
1
23
24
25
26
27
28
29
30
DVDD
OMCLK
SDTO
OBICK
OLRCK
DVSS
AVDD
9
10
11
12
13
14
20
21
22
CMODE2
17
18
19
OBIT1
IMCLK
CMODE0
ODIF0
ODIF1
CMODE1
16
OBIT0
UNLOCK
15
[AK4127]
MS0593-J-02 2010/05
- 4 -
■ AK4125
Item AK4125 AK4127
TDM Mode - X
Slave mode for Bypass mode -
X
OMCLK pin OMCLK
Normal mode: OMCLK
TDM mode: TDMIN
192fso for Output PORT (Master Mode) X
-
(-: Not available, X: Available)
[AK4127]
MS0593-J-02 2010/05
- 5 -
No. Pin Name I/O Function
1 FILT O PLL Loop Filter Pin, Hi-Z when PDN pin = “L”.
2 AVSS - Analog Ground Pin
3 PDN I
Power-Down Mode Pin
“H”: Power up, “L”: Power down reset and initializes the control register.
4 SMUTE I
Soft Mute Pin
“H”: Soft Mute, “L”: Normal Operation
5 DITHER I
Dither Enable Pin
“H”: Dither ON, “L”: Dither OFF
6 PLL2 I PLL Mode Select 2 Pin
7 ILRCK I/O Input Channel Clock Pin, Output “L” when PDN = “L” and master mode.
8 IBICK I/O Audio Serial Data Clock Pin, Output “L” when PDN = “L” and master mode.
9 SDTI I Audio Serial Data Input Pin
10 IDIF0 I Audio Interface Format 0 Pin for Input PORT
11 IDIF1 I Audio Interface Format 1 Pin for Input PORT
12 IDIF2 I Audio Interface Format 2 Pin for Input PORT
13 PLL0 I PLL Mode Select 0 Pin
14 PLL1 I PLL Mode Select 1 Pin
15 UNLOCK O Unlock Status Pin, Output “H” when PDN = “L”
16 OBIT0 I Bit Length Select 0 Pin for Output Data
17 OBIT1 I Bit Length Select 1 Pin for Output Data
18 IMCLK I Master Clock Input Pin for Input PORT
19 CMODE0 I Clock Mode Select 0 Pin
20 CMODE1 I Clock Mode Select 1 Pin
21 CMODE2 I Clock Mode Select 2 Pin
22 ODIF0 I Audio Interface Format 0 Pin for Output PORT
23 ODIF1 I Audio Interface Format 1 Pin for Output PORT
24 SDTO O Audio Serial Data Output Pin for Output PORT, Output “L” when PDN pin = “L”
25 OBICK I/O
Audio Serial Data Clock Pin for Output PORT
Output “L” when PDN = “L” and master mode.
26 OLRCK I/O
Output Channel Clock Pin for Output PORT
Output “L” when PDN = “L” and master mode.
27 OMCLK I
Master Clock/TDM Data Input Pin for Output PORT
OMCLK: Master Clock Input Pin (except for PLL2/1/0 pin = “L/H/H”)
TDMIN: TDM Data Input Pin (PLL2/1/0 pin = “L/H/H”)
28 DVDD - Digital Power Supply Pin, 3.0 ∼ 3.6V
29 DVSS - Digital Ground Pin
30 AVDD - Analog Power Supply Pin, 3.0 ∼ 3.6V
Note: All input pins should not be left floating.
[AK4127]
MS0593-J-02 2010/05
- 6 -
■
Analog FILT
SMUTE, DITHER
DVSS
IMCLK, OMCLK
DVSS @
Digital
UNLOCK
(AVSS, DVSS=0V; Note 1)
Parameter Symbol min max Units
Power Supplies:
Analog
Digital
|AVSS − DVSS| (
Note 2)
AVDD
DVDD
ΔGND
−0.3
−0.3
-
4.6
4.6
0.3
V
V
V
Input Current, Any Pin Except Supplies IIN - ±10 mA
Digital Input Voltage (Note 3) VIND −0.3 DVDD+0.3 V
Ambient Temperature (Power applied) Ta −40 85 °C
Storage Temperature Tstg −65 150 °C
Note 1.
Note 2. AVSS, DVSS
Note 3. PND, SMUTE, DITHER, PLL2, ILRCK, IBICK, SDTI, IDIF0, IDIF1, IDIF2, PLL0, PLL1, OBIT0, OBIT1,
IMCLK, CMODE0, CMODE1, CMODE2, ODIF0, ODIF1, OBICK, OLRCK and OMCLK
:
(AVSS, DVSS=0V; Note 1)
Parameter Symbol min typ max Units
Power Supplies
(
Note 4)
Analog
Digital
AVDD
DVDD
3.0
3.0
3.3
3.3
3.6
AVDD
V
V
Note 4. AVDD DVDD
:
[AK4127]
MS0593-J-02 2010/05
- 7 -
SRC
(Ta=25°C; AVDD=DVDD=3.3V; AVSS=DVSS=0V; data=24bit; measurement bandwidth = 20Hz ~ FSO/2; unless
otherwise specified.)
Parameter Symbol min typ max Units
SRC Characteristics:
Resolution 24 Bits
Input Sample Rate
FSI 8 216 kHz
Output Sample Rate FSO 8 216 kHz
THD+N (Input = 1kHz, 0dBFS, Note 5)
FSO/FSI = 44.1kHz/48kHz
FSO/FSI = 48kHz/44.1kHz
FSO/FSI = 48kHz/192kHz
FSO/FSI = 192kHz/48kHz
Worst Case (FSO/FSI = 32kHz/176.4kHz)
-
-
-
-
-
−130
−124
−133
−124
-
-
-
-
-
−91
dB
dB
dB
dB
dB
Dynamic Range (Input = 1kHz, −60dBFS, Note 5)
FSO/FSI = 44.1kHz/48kHz
FSO/FSI = 48kHz/44.1kHz
FSO/FSI = 48kHz/192kHz
FSO/FSI = 192kHz/48kHz
Worst Case (FSO/FSI = 48kHz/32kHz)
Dynamic Range (Input = 1kHz, −60dBFS, A-weighted,
Note 5)
FSO/FSI = 44.1kHz/48kHz
-
-
-
-
132
-
136
136
136
132
-
140
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
Ratio between Input and Output Sample Rate FSO/FSI 1/6 6 -
Note 5. Audio Precision System Two Cascade
[AK4127]
MS0593-J-02 2010/05
- 8 -
(Ta=25°C; AVDD, DVDD=3.0 ∼ 3.6V)
Parameter Symbol min typ max Units
Digital Filter
0.985 ≤ FSO/FSI ≤ 6.000 PB 0
0.4583FSI
kHz
0.905 ≤ FSO/FSI < 0.985 PB 0
0.4167FSI
kHz
0.714 ≤ FSO/FSI < 0.905 PB 0
0.3195FSI
kHz
0.656 ≤ FSO/FSI < 0.714 PB 0
0.2852FSI
kHz
0.536 ≤ FSO/FSI < 0.656 PB 0
0.2182FSI
kHz
0.492 ≤ FSO/FSI < 0.536 PB 0
0.2177FSI
kHz
0.452 ≤ FSO/FSI < 0.492 PB 0
0.1948FSI
kHz
0.357 ≤ FSO/FSI < 0.452 PB 0
0.1458FSI
kHz
0.324 ≤ FSO/FSI < 0.357 PB 0
0.1302FSI
kHz
0.246 ≤ FSO/FSI < 0.324 PB 0
0.0917FSI
kHz
0.226 ≤ FSO/FSI < 0.246 PB 0
0.0826FSI
kHz
Passband −0.01dB
0.1667 ≤ FSO/FSI < 0.226 PB 0
0.0583FSI
kHz
0.985 ≤ FSO/FSI ≤ 6.000 SB 0.5417FSI kHz
0.905 ≤ FSO/FSI < 0.985 SB 0.5021FSI kHz
0.714 ≤ FSO/FSI < 0.905 SB 0.3965FSI kHz
0.656 ≤ FSO/FSI < 0.714 SB 0.3643FSI kHz
0.536 ≤ FSO/FSI < 0.656 SB 0.2974FSI kHz
0.492 ≤ FSO/FSI < 0.536 SB 0.2813FSI
kHz
0.452 ≤ FSO/FSI < 0.492 SB 0.2604FSI
kHz
0.357 ≤ FSO/FSI < 0.452 SB 0.2116FSI
kHz
0.324 ≤ FSO/FSI < 0.357 SB 0.1969FSI
kHz
0.246 ≤ FSO/FSI < 0.324 SB 0.1573FSI
kHz
0.226 ≤ FSO/FSI < 0.246 SB 0.1471FSI
kHz
Stopband
0.1667 ≤ FSO/FSI < 0.226 SB 0.1020FSI
kHz
Passband Ripple PR ±0.01 dB
0.985 ≤ FSO/FSI ≤ 6.000 SA 121.2 dB
0.905 ≤ FSO/FSI < 0.985 SA 121.4 dB
0.714 ≤ FSO/FSI < 0.905 SA 115.3 dB
0.656 ≤ FSO/FSI < 0.714 SA 116.9 dB
0.536 ≤ FSO/FSI < 0.656 SA 114.6 dB
0.492 ≤ FSO/FSI < 0.536 SA 100.2 dB
0.452 ≤ FSO/FSI < 0.492 SA 103.3 dB
0.357 ≤ FSO/FSI < 0.452 SA 102.0 dB
0.324 ≤ FSO/FSI < 0.357 SA 103.6 dB
0.246 ≤ FSO/FSI < 0.324 SA 104.0 dB
0.226 ≤ FSO/FSI < 0.246 SA 103.3 dB
Stopband
Attenuation
0.1667 ≤ FSO/FSI < 0.226 SA 73.2 dB
Group Delay (Note 6) GD - 56 - 1/fs
Note 6. L, R ILRCK
L, R OLRCK
[AK4127]
MS0593-J-02 2010/05
- 9 -
DC
(Ta=25°C; AVDD, DVDD=3.0 ∼ 3.6V)
Parameter Symbol min typ max Units
High-Level Input Voltage
Low-Level Input Voltage
VIH
VIL
70%DVDD
-
-
-
-
30%DVDD
V
V
High-Level Output Voltage (Iout=−400μA)
Low-Level Output Voltage (Iout=400μA)
VOH
VOL
DVDD−0.4
-
-
-
-
0.4
V
V
Input Leakage Current Iin - - ±10 μA
Power Supplies
Power Supply Current
Normal operation (PDN pin = “H”)
FSI=FSO=48kHz at Slave Mode: AVDD=DVDD=3.3V
FSI=FSO=192kHz at Master Mode: AVDD=DVDD=3.3V
: AVDD=DVDD=3.6V
Power down (PDN pin = “L”) (
Note 7)
AVDD+DVDD
15
65
10
100
100
mA
mA
mA
μA
Note 7. DVSS
(Ta=25°C; AVDD, DVDD=3.0 ∼ 3.6V; C
L
=20pF)
Parameter Symbol min typ max Units
Master Clock Timing
Frequency
Pulse Width Low
Pulse Width High
fCLK
tCLKL
tCLKH
1.024
0.4/fCLK
0.4/fCLK
41.472
MHz
ns
ns
LRCK for Input data (ILRCK)
Frequency
Duty Cycle Slave Mode
Master Mode
fs
Duty
Duty
8
48
50
50
216
52
kHz
%
%
LRCK for Output data (OLRCK)
Frequency
Duty Cycle Slave Mode
Master Mode
fs
Duty
Duty
8
48
50
50
216
52
kHz
%
%
LRCK for TDM256 Mode (OLRCK)
Frequency
“H” time
“L” time
fs
tLRH
tLRL
8
1/256fs
1/256fs
48
kHz
ns
ns
Audio Interface Timing
Input PORT (Slave mode)
IBICK Period (8kHz ∼ 54kHz)
(54kHz ∼ 108kHz)
(108kHz ∼ 216kHz)
IBICK Pulse Width Low
Pulse Width High
ILRCK Edge to IBICK “↑” (
Note 8)
IBICK “↑” to ILRCK Edge (
Note 8)
SDTI Hold Time from IBICK “↑”
SDTI Setup Time to IBICK “↑”
tBCK
tBCK
tBCK
tBCKL
tBCKH
tLRB
tBLR
tSDH
tSDS
1/256fs
1/128fs
1/64fs
27
27
15
15
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
[AK4127]
MS0593-J-02 2010/05
- 10 -
Input PORT (Master mode)
IBICK Frequency
IBICK Duty
IBICK “↓” to ILRCK
SDTI Hold Time from IBICK “↑”
SDTI Setup Time to IBICK “↑”
fBCK
dBCK
tMBLR
tSDH
tSDS
−20
15
15
64fs
50
20
Hz
%
ns
ns
ns
Output PORT (Slave mode)
OBICK Period (8kHz ∼ 54kHz)
(54kHz ∼ 108kHz)
(108kHz ∼ 216kHz)
OBICK Pulse Width Low
Pulse Width High
OLRCK Edge to OBICK “↑” (
Note 8)
OBICK “↑” to OLRCK Edge (
Note 8)
OLRCK to SDTO (MSB) (Except I
2
S mode)
OBICK “↓” to SDTO
tBCK
tBCK
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
1/256fs
1/128fs
1/64fs
27
27
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
Output PORT (TDM256 slave mode)
OBICK Period
OBICK Pulse Width Low
Pulse Width High
OLRCK Edge to BICK “↑” (
Note 8)
OBICK “↑” to LRCK Edge (
Note 8)
OBICK “↓” to SDTO
TDMIN Hold Time from OBICK “↑”
TDMIN Setup Time to OBICK “↑”
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSD
tSDH
tSDS
81
32
32
20
20
20
10
20
ns
ns
ns
ns
ns
ns
ns
ns
Output PORT (Master mode)
OBICK Frequency
OBICK Duty
OBICK “↓” to OLRCK
OBICK “↓” to SDTO
fBCK
dBCK
tMBLR
tBSD
−20
−20
64fs
50
20
20
Hz
%
ns
ns
Reset Timing
PDN Pulse Width (
Note 9)
tPD
150
ns
Note 8. LRCK BICK “↑”
Note 9. AK4127 PDN pin = “L”
[AK4127]
MS0593-J-02 2010/05
- 11 -
■
1/fCLK
MCLK
tCLKH tCLKL
VIH
VIL
1/fs
LRCK
VIH
VIL
tBCK
BICK
tBCKH tBCKL
VIH
VIL
Clock Timing
LRCK
VIH
VIL
tBLR
BICK
VIH
VIL
tLRS
SDTO 50%DVDD
tLRB
tBSD
tSDS
SDTI
VIL
tSDH
VIH
Audio Interface Timing (Slave mode)
Note : BICK IBICK, OBICK LRCK ILRCK, OLRCK
[AK4127]
MS0593-J-02 2010/05
- 12 -
LRCK
BICK 50%DVDD
SDTO 50%DVDD
tBSD
tSDS
SDTI
VIL
tSDH
VIH
tMBLR
dBCK
50%DVDD
Audio Interface Timing (Master mode)
Note : BICK IBICK, OBICK LRCK ILRCK, OLRCK
tPD
PDN
VIL
Power Down & Reset Timing
[AK4127]
MS0593-J-02 2010/05
- 13 -
■
ILRCK PLL (
Table 2 Mode 0 ∼ 3) IBICK PLL
(
Table 2 Mode 4 ∼ 7) IMCLK
(
Table 2 Mode 8 ∼ 15) MCLK
/ PLL IDIF2-0 pin PLL2-0 pin PDN pin = “L”
PLL2-0 pin= “L/H/H” (CMODE2-0pin = “H/L/L” or
“H/H/L”) TDM
IDIF2-0 pin MSB
2’s SDTI IBICK
PDN pin = “L”
Mode IDIF2 IDIF1 IDIF0 SDTI Format ILRCK IBICK IBICK Freq Master / Slave
0 L L L 16bit, LSB justified
≥ 32fsi
1 L L H 20bit, LSB justified
≥ 40fsi
2 L H L 24/20bit, MSB justified
≥ 48fsi
3 L H H 24/16bit, I
2
S Compatible
≥ 48fsi or 32fsi
4 H L L 24bit, LSB justified
Input Input
≥ 48fsi
Slave
5 H L H 24bit, MSB justified 64fsi
6 H H L 24bit, I
2
S Compatible
Output Output
64fsi
Master
7 H H H Reserved
Table 1. Input Audio Interface Format (Input PORT)
Mode Master / Slave PLL2 PLL1 PLL0 ILRCK Freq IBICK Freq IMCLK
SMUTE
(
Note 14)
0 L L L
8k ∼ 96kHz
1 L L H
Manual
2 L H L
Semi-Auto
3 L H H
8k ∼ 216kHz
16k ∼ 216kHz
(
Note 10)
Depending
on IDIF2-0
(
Note 11)
Not
needed.
(
Note 13)
Manual
4 H L L
32fsi
(
Note 12)
5 H L H 64fsi
6 H H L 128fsi
Manual
7
Slave
IMCLK = DVSS
IBICK = Input
ILRCK = Input
H H H
8k ∼ 216kHz
(
Note 11)
64fsi
Not
needed.
(
Note 13)
Semi-Auto
8 L L L
8k ∼ 216kHz
128fsi
9 L L H
8k ∼ 108kHz
256fsi
10 L H L
8k ∼ 54kHz
512fsi
Manual
11 L H H
8k ∼ 216kHz
128fsi
Semi-Auto
12 H L L
8k ∼ 216kHz
192fsi
13 H L H
8k ∼ 108kHz
384fsi
14 H H L
8k ∼ 54kHz
768fsi
Manual
15
Master
IMCLK = Input
IBICK = Output
ILRCK = Output
H H H
8k ∼ 216kHz
64fsi
192fsi
Semi-Auto
Table 2. PLL Setting (Input PORT)
Note 10. FILT pin R C PLL PLL
Note 11. IBICK
Note 12. IBICK = 32fsi 16bit LSB justified 16bit I
2
S Compatible
Note 13. DVSS
Note 14. SMUTE Manual Semi-Auto
[AK4127]
MS0593-J-02 2010/05
- 14 -
ILRCK
IBICK(32fs)
0 1102 3 9 1112131415 0 123 10109 1112131415
SDTI(i)
Don't Care 1 0 15 14 13 21015 14 13 12 12Don't Care
15:MSB, 0:LSB
SDTI(i)
15 14 13 7654321015 14 13 1576543210
IBICK(64fs)
0 1182 3 19 20 31 0 1 2 3 1018 19 20 3117 17
Lch Data Rch Data
Figure 1. Mode 0 Timing
ILRCK
IBICK(64fs)
0 1 22431012 103124
SDTI(i)
Don't Care 0 8 10
19:MSB, 0:LSB
Lch Data Rch Data
19 8 Don't Care 191
12 13 1312
Figure 2. Mode 1 Timing
ILRCK
IBICK(64fs)
0 1 220212431012 102220 21 312422 23 23
SDTI(i)
Don't Care0 0
23:MSB, 0:LSB
Lch Data Rch Data
Don't Care
432123 22 23 22 231234
Figure 3. Mode 2, 5 Timing (24bit MSB)
ILRCK
IBICK(64fs)
0 1 22521 24 0 12 1022 2521 2422 23 233
SDTI(i)
Don't Care0 0
23:MSB, 0:LSB
Lch Data Rch Data
Don't Care
432123 22 23 22 1234
Figure 4. Mode 3, 6 Timing (24bit I
2
S)
[AK4127]
MS0593-J-02 2010/05
- 15 -
ILRCK
IBICK(64fs)
0 1 22431012 10312489 89
SDTI(i)
Don't Care 0 8 10
23:MSB, 0:LSB
Lch Data Rch Data
23 8 Don't Care 231
Figure 5. Mode 4 Timing
■
MCLK
/ SRC CMODE2-0 pin
PDN pin = “L”
ODIF1-0 pin OBIT1-0 pin
MSB 2’s SDTO OBICK
PDN pin = “L”
IBICK=OBICK=64fs IBICK OBICK
PLL2-0 pin= “L/H/H” (CMODE2-0pin = “H/L/L” or “H/H/L”)
TDM TDM OMCLK pin TDM TDMIN
pin
Mode CMODE2 CMODE1 CMODE0 Master / Slave OMCLK fso
0 L L L Master 256fso
8k ∼ 108kHz
1 L L H Master 384fso
8k ∼ 108kHz
2 L H L Master 512fso
8k ∼ 54kHz
3 L H H Master 768fso
8k ∼ 54kHz
4 H L L Slave
Not used. Set to DVSS.
(
Note 15)
8k ∼ 216kHz
5 H L H Master 128fso
8k ∼ 216kHz
6 H H L Slave (Bypass)
Not used. Set to DVSS.
(
Note 15)
8k ∼ 216kHz
7 H H H Master (Bypass) Not used. Set to DVSS.
8k ∼ 216kHz
Note 15 PLL2-0 pin= “L/H/H” TDMIN
Table 3. Master/Slave Control (Output PORT)
Mode ODIF1 ODIF0 SDTO Format
0 L L LSB justified
1 L H (Reserved)
2 H L MSB justified
3 H H I
2
S Compatible
Table 4. Output Audio Interface Format 1 (Output PORT)
[AK4127]
MS0593-J-02 2010/05
- 16 -
OBICK Frequency
Mode Master / Slave OBIT1 OBIT0 SDTO OLRCK OBICK
MSB justified, I
2
S
LSB
justified
0 L L 16bit
≥ 32fso
1 L H 18bit
≥ 36fso
2 H L 20bit
≥ 40fso
3
Slave
CMODE2-0 =
“HLL” or
“HHL”
H H 24bit
Input Input
≥ 48fso
64fso
4 L L 16bit
5 L H 18bit
6 H L 20bit
7
Master
CMODE2-0 =
“HLL” or
“HHL”
H H 24bit
Output Output 64fso
Table 5. Output Audio Interface Format 2 (Output PORT)
OLRCK
OBICK(64fs)
0 1
Lch Data Rch Data
89
SDTO(O)
15:MSB, 0:LSB
SDTO(O)
17:MSB, 0:LSB
SDTO(O)
19:MSB, 0:LSB
SDTO(O)
23:MSB, 0:LSB
1
012 13 141110 16 1715 20 21 22 2923 3130
10 9 81115 14 2 1 0
10 9 81115 14 2 1 017 16
10 9 81115 14 2 1 017 1619 18
10 9 81115 14 2 1 017 1619 1821 2023 22
12 13 14118 9 10 16 1715 20 21 22 2923 3130 0 1 2
10 9 21115 14 018
2815 14 11 0117 16 10 9
2815 14 9 0117 1619 18 11 10
2815 11 10 9 0117 1619 1821 2023 22 14
Figure 6. Normal Mode LSB Timing
OLRCK
OBICK(64fs)
0 1 2
Lch Data Rch Data
34
SDTO(O)
SDTO(O)
SDTO(O)
SDTO(O)
23:MSB, 0:LSB
34
15:MSB, 0:LSB
17:MSB, 0:LSB
19:MSB, 0:LSB
32148765 010 921 2023 22
321465 017 1619 18
321415 14 017 16
15 14 13 12 2 1 0
32148765 010 921 2023 22
321465 017 1619 18
321415 14 017 16
15 14 13 12 2 1 0
031 1 2 031 1 2
191817 2413 14 1615 20 21 2322 191817 2413 14 1615 20 21 2322
23 22
19 18
17 16
15 14
Figure 7. Normal Mode MSB Timing
OLRCK
OBICK(64fs)
0 1 2
Lch Data Rch Data
34
SDTO(O)
SDTO(O)
SDTO(O)
SDTO(O)
23:MSB, 0:LSB
34
15:MSB, 0:LSB
17:MSB, 0:LSB
19:MSB, 0:LSB
012 031 1 2191817 2414 1615 20 21 2322 191817 2414 1615 20 21 2322
23
19
17
1515 14 13 12 2 1 0
321415 14 017 16
321465 017 1619 18
32148765 010 921 2023 22
15 14 13 12 2 1 0
321415 14 017 16
321465 017 1619 18
32148765 010 921 2023 22
Figure 8. Normal mode I
2
S Compatible Timing
[AK4127]
MS0593-J-02 2010/05
- 17 -
23
OLRCK(I)
OBICK (I: 256fso)
SDTO(O)
22 0
L1
32 BICK
256 OBICK
22 0
R1
32 BICK
2223 23
23
TDMIN(I)
22 0
L2
22 0
R2
2223 23
23 22 0
L2
32 BICK
22 0
R2
32 BICK
23
23 22 0
L3
22 0
R3
23 23 22 0
L4
22 0
R4
23
23 22 0
L3
22 0
R3
23 23 22 0
L4
22 0
R4
23
Figure 9. TDM mode MSB Timing
OLRCK(I)
OBICK (I: 256fso)
SDTO(O)
23 0
L1
32 BICK
256 OBICK
23 0
R1
32 BICK
23
TDMIN(I)
23 0
L2
23 0
R2
23
23 0
L2
32 BICK
23 0
R2
32 BICK
23 0
L3
23 0
R3
23
0
L4
23
0
R4
23 0
L3
23 0
R3
23 0
L4
23 0
R4
Figure 10. TDM mode I
2
S Compatible Timing
[AK4127]
MS0593-J-02 2010/05
- 18 -
■ TDM
AK4127 TDM 4 (8ch )
#1 SDTO pin #2 OMCLK (TDMIN) pin #2 SDTO
pin #1 2 #2 2 4 TDM
Figure 11
48kHz
256fs
(TDMIN of AK4127 #3)
OLRC
K
AK4127 #1
OBIC
K
TDMIN
SDTO
OMCL
K
256fs or 512fs
GND
OLRC
K
AK4127 #2
OBIC
K
TDMIN
SDTO
OMCL
K
Figure 11. Cascade TDM Connection Diagram
OLRCK
OBICK(256fs)
#1 SDTO(o)
33 0
L #1
32 BICK
256 BICK
22 0
R #1
32 BICK
23 23
= #2 TDMIN(i)
22 0
L #4
32 BICK
22 0
R #4
32 BICK
22 23 23 23 22 0
L #3
32 BICK
22 0
R #3
32 BICK
23 23 22 0
L #2
32 BICK
22 0
R #2
32 BICK
23 23 22 0
L #1
32 BICK
22 0
R #1
32 BICK
23 23
#2 SDTO(o)
= #3 TDMIN(i)
#3 SDTO(o)
= #4 TDMIN(i)
#4 SDTO(o)
22 0
L #3
32 BICK
22 0
R #3
32 BICK
23 23 22 0
L #2
32 BICK
22 0
R #2
32 BICK
23 23 22 0
L #1
32 BICK
22 0
R #1
32 BICK
23 23 22 23
22 0
L #2
32 BICK
22 0
R #2
32 BICK
23 23 22 0
L #1
32 BICK
22 0
R #1
32 BICK
23 23 22 23
22 23
Figure 12. Cascade TDM Timing (4devices)
[AK4127]
MS0593-J-02 2010/05
- 19 -
■
1. Manual
SRC SMUTE pin
SMUTE pin “H” 1024OLRCK SRC −∞ (“0”)
SMUTE pin “L” −∞ −∞ 1024OLRCK 0dB
1024OLRCK
0dB
SMUTE
Attenuation
0dB
-∞
(1)
(2)
SDTO
1024/fso
Figure 13. Soft Mute Function (Manual Mode)
(1) 1024OLRCK (1024/fso) −∞ (“0”)
(2) 1024OLRCK
0dB
2. Semi-Auto
PLL2-0 pin (
Table 2 ) (PDN pin = “L” → “H”)
4410/fso=100ms@fso=44.1kHz
SMUTE pin “H”
PDN pin
Attenuation
0dB
-∞
SDTO
4410/fso
(1)
SMUTE pin
Don’t care
“L”
“L”
Figure 14. Soft Mute Function (Semi-Auto Mode)
(1) 1024OLRCK (1024/fso) 0dB
[AK4127]
MS0593-J-02 2010/05
- 20 -
■
AK4127 SRC SRC DITHER
pin “H” OBIT1-0 pin
■
AK4127 PDN pin “L”
PDN pin = “L” SDTO “L” PDN pin “L”
100ms “L”
Case 1
External clocks
(Input port)
SDTI
Don’t care
SDTO
(Internal state)
Power-down
Normal
operation
PLL lock &
fs detection
< 100ms
Normal data
Input Clocks 1
External clocks
(Output port)
Don’t care
Don’t care
PDN
Power-down
Don’t care
Don’t care
Don’t care
“0” data
Normal
operation
PLL lock &
fs detection
< 100ms
Normal data
PD
Input Data 1
Output Clocks 1
Input Clocks 2
Input Data 2
Output Clocks 2
“0” data
“0” data
UNLOCK
Figure 15. System Reset 1
Case 2
External clocks
(Input port)
SDTI
SDTO
(Internal state)
Power-down
Normal
operation
PLL lock &
fs detection
< 100ms
Normal data
(No Clock)
External clocks
(Output port)
PDN
Power-down
Don’t care
Don’t care
Don’t care
“0” data
PLL Unlock
Input Clocks
Input Data
Output Clocks
“0” data
(Don’t care)
(Don’t care)
UNLOCK
Figure 16. System Reset 2
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