[AKD4129-A]
<KM103600> 2010/06
- 1 -
AKD4129-A AK4129
AKD4129-A --- AK4129
IBM-AT
Windows NT
• DIT, DIR or COAX
• 10
O pt In AK4114
(
DIR
)
10pin
Header
5V GND
Opt Out AK4114
(
DIT
)
10pin
Header
AK4129
COAX
Regulator
COAX
O pt In AK4114
(
DIR
)
10pin
Header
COAX
O pt In AK4114
(
DIR
)
10pin
Header
COAX
DVDDAV D D
Regulator
Regulator
D3.3V-1
D3.3V-2
10pin
Header
(
I
2
C
)
Figure 1. AKD4129-A
*
A
KD4129-
A
A
K4129 Rev.0
[AKD4129-A]
<KM103600> 2010/06
- 2 -
[1]
Typ
Default
+5V
+5V
T1,T2,T3
AK4129 AVDD DVDD
AK4114
+5V
AVDD
+3.3V
AK4129 AVDD
T1
AVDD AK4129
AVDD
JP1 AVDD
Open
DVDD
+3.3V
AK4129 DVDD
T1
DVDD AK4129
DVDD
JP2 DVDD
Open
D3.3V-1
+3.3V
AK4114
T2
AK4114
JP3 D3.3V-1
Open
D3.3V-2
+3.3V
AK4114
T3
AK4114
JP4 D3.3V-2
Open
GND
0V
GND
Table 1.
[AKD4129-A]
<KM103600> 2010/06
- 3 -
[2]
(1). AK4129 AVDD
(a) AVDD (b) REG
AVDD-SEL
JP1
AVDD REG
3
AVDD-SEL
JP1
AVDD REG
3
(2). AK4129 DVDD
(a) DVDD (b) REG
DVDD-SEL
JP2
REG DVDD
3
DVDD-SEL
JP2
REG DVDD
3
(3). D3.3V-1 (AK4114 )
(a) D3.3V-1 (b) REG
D3.3V-1 SEL
JP3
D3.3V-1 REG
3
D3.3V-1 SEL
JP3
D3.3V-1 REG
3
(4). D3.3V-2 (AK4114 )
(a) D3.3V-2 (b) REG
D3.3V-2 SEL
JP4
REG D3.3V-2
3
D3.3V-2 SEL
JP4
REG D3.3V-2
3
[AKD4129-A]
<KM103600> 2010/06
- 4 -
[3] DIP ( )
(1).
(1)-1. AK4114 (U2,U3,U4) DIR (Default)
(1)-2. 10 (PORT1,2,3)
(2).
(2)-1. AK4114 (U6) DIT (Default)
(2)-2. 10 (PORT5)
(3).
[4]
AK4129 (U1), AK4114 (U2,U3,U4), AK4114 (U6)
SW2,SW10,SW11,SW12,SW14 “L”
AK4129 (U1), AK4114 (U2,U3 ,U4), AK4114 (U6) “H”
[AKD4129-A]
<KM103600> 2010/06
- 5 -
DIP
(1). DIP
(1)-1. AK4114 (U2,U3,U4) DIR (Default)
(1)-1-1. RX
RX JP26 (U2), JP32(U3), JP36(U4)
(a) RX Optical (Default) (b) RX BNC
INPUTx SEL
BNC OPT
3
INPUTx SEL
BNC OPT
3
x 1 3 INPUT1 SEL INPUT3 SEL
(1)-1-2. IBICK1 3, ILRCK1 3, SDTI1 3
10 (PORT1 3)
IBICKx SDTIxILRCKx
IMCLK-SEL
JP27
EXT
DSP1
DIR
2
x 1 3
[AKD4129-A]
<KM103600> 2010/06
- 6 -
(1)-1-3. SDTI1, SDTI2, SDTI3
AK4129 (U1) SDTI1, SDTI2, SDTI3
(a) (INAS pin = “L”) (Default)
SDTI1-SEL
JP5
A
synchronous
Synchronous
GND
SDTI2-SEL
JP6
A
synchronous
Synchronous
GND
SDTI3-SEL
JP7
A
synchronous
Synchronous
GND
SDTI4-SEL
JP8
A
synchronous
Synchronous
GND
2
5
6
2
5
6
2
5
6
2
5
6
(b) (INAS pin = “H”)
SDTI1-SEL
JP5
A
synchronous
Synchronous
GND
SDTI2-SEL
JP6
A
synchronous
Synchronous
GND
SDTI3-SEL
JP7
A
synchronous
Synchronous
GND
SDTI4-SEL
JP8
A
synchronous
Synchronous
GND
2
5
6
2
5
6
2
5
6
2
5
6
(c) SDTI1,SDTI2,SDTI3 GND
SDTI1-SEL
JP5
A
synchronous
Synchronous
GND
SDTI2-SEL
JP6
A
synchronous
Synchronous
GND
SDTI3-SEL
JP7
A
synchronous
Synchronous
GND
SDTI4-SEL
JP8
A
synchronous
Synchronous
GND
2
5
6
2
5
6
2
5
6
2
5
6
[AKD4129-A]
<KM103600> 2010/06
- 7 -
(1)-2. 10 (PORT1 3)
(1)-2-1. RX
PORT6 8 (OPT), BNC J1 3(COAX)
(1)-2-2. IBICK1 3, ILRCK1 3, SDTI1 3
( IBICK, ILRCK) ( SDTI) 10
AK4129 (U1)
IBICKx SDTIxILRCKx
IMCLK-SEL
JP27
EXT
DSP1
DIR
2
x 1 3
(1)-2-3. SDTI1, SDTI2, SDTI3
AK4129 (U1) SDTI1, SDTI2, SDTI3
(a) (INAS pin = “L”) (Default)
SDTI1-SEL
JP5
A
synchronous
Synchronous
GND
SDTI2-SEL
JP6
A
synchronous
Synchronous
GND
SDTI3-SEL
JP7
A
synchronous
Synchronous
GND
SDTI4-SEL
JP8
A
synchronous
Synchronous
GND
2
5
6
2
5
6
2
5
6
2
5
6
(b) (INAS pin = “H”)
SDTI1-SEL
JP5
A
synchronous
Synchronous
GND
SDTI2-SEL
JP6
A
synchronous
Synchronous
GND
SDTI3-SEL
JP7
A
synchronous
Synchronous
GND
SDTI4-SEL
JP8
A
synchronous
Synchronous
GND
2
5
6
2
5
6
2
5
6
2
5
6
(c) SDTI1,SDTI2,SDTI3 GND
SDTI1-SEL
JP5
A
synchronous
Synchronous
GND
SDTI2-SEL
JP6
A
synchronous
Synchronous
GND
SDTI3-SEL
JP7
A
synchronous
Synchronous
GND
SDTI4-SEL
JP8
A
synchronous
Synchronous
GND
2
5
6
2
5
6
2
5
6
2
5
6
[AKD4129-A]
<KM103600> 2010/06
- 8 -
(2). DIP
(2)-1. AK4114 (U6) DIT (Default)
(2)-1-1. TX
TX JP44 (OUTPUT SEL)
(a) TX Optical (Default) (b) TX BNC
OUTPUT SEL
JP44
3
BNC OPT
OUTPUT SEL
JP44
BNC OPT
3
(2)-1-2. XTI
AK4129(U1) XTI/OMCLKpin AK4114 (U6) XTIpin JP51 (DIT-OMCKO), JP52
(EXT-CLK), JP53(SEL3), JP20(MCKO), JP45(DIT-OMCLK SEL)
(a) X1 ( X2 )
JP5
2
EXT-CLK
DIT-OMCKO SEL
JP51
3
2 4
AK4128
EX
T
JP45
DIT-OMCLK SEL
DIT
DSP5
EXT
2
5
6
JP53
SEL3
3
GND
OMCLK
JP20
MCKO
(b) X2 ( X1 )
JP5
2
EXT-CLK
DIT-OMCKO SEL
JP51
3
2 4
AK4128
EXT
JP45
DIT-OMCLK SEL
DIT
DSP5
EXT
2
5
6
JP53
SEL3
3
GND
OMCLK
JP20
MCKO
(c) XTI J8 (EXT-CLK) ( X1, X2 )
JP5
2
EXT-CLK
DIT-OMCKO SEL
JP51
3
2 4
AK4128
EXT
JP45
DIT-OMCLK SEL
DIT
DSP5
EXT
2
5
6
JP53
SEL3
3
GND
OMCLK
JP20
MCKO
[AKD4129-A]
<KM103600> 2010/06
- 9 -
(2)-1-3. OBICK, OLRCK, SDTO
(2)-1-3-1. OBICK, OLRCK AK4114(U6, DIT) SDTO AK4129(U1)
10 PORT5 (DSP5)
JP48
OBICK
JP49
SDTO
JP50
OLRCK
JP46
DIT-OBICK SEL
JP47
DIT-OLRCK SEL
DIT-Slave
DIT-Master
DIT-Slave
DIT-Master
2
3
4
2
3
4
JP18
AK4128-OBICK SEL
JP19
AK4128-OLRCK SEL
A
K4128-Slave
A
K4128-Master
A
K4128-Slave
A
K4128-Master
2
3
4
2
3
4
(2)-1-3-2. OBICK, OLRCK, SDTO AK4129(U1)
10 PORT5 (DSP5)
JP48
OBICK
JP49
SDTO
JP50
OLRCK
JP46
DIT-OBICK SEL
JP47
DIT-OLRCK SEL
DIT-Slave
DIT-Master
DIT-Slave
DIT-Master
2
3
4
2
3
4
JP18
AK4128-OBICK SEL
JP19
AK4128-OLRCK SEL
A
K4128-Slave
A
K4128-Master
A
K4128-Slave
A
K4128-Master
2
3
4
2
3
4
[AKD4129-A]
<KM103600> 2010/06
- 10 -
(2)-1-4. AK4114(U6, DIT)
(a) SDTO1 (b)SDTO2 (c)SDTO3
SDTO-SEL
JP17
2
3
4
2
SDTO
1
SDTO-SEL
JP17
2
3
4
2
SDTO
1
SDTO-SEL
JP17
2
3
4
2
SDTO
1
SDTO4
(2)-2. 10 (PORT5)
(2)-2-1. TX
PORT10 (OPT), BNC J5 (COAX)
(2)-2-2. OBICK, OLRCK, SDTO
(2)-2-2-1. OBICK, OLRCK SDTO AK4129(U1)
JP48
OBICK
JP49
SDTO
JP50
OLRCK
JP46
DIT-OBICK SEL
JP47
DIT-OLRCK SEL
DIT-Slave
DIT-Master
DIT-Slave
DIT-Master
2
3
4
2
3
4
JP18
AK4128-OBICK SEL
JP19
AK4128-OLRCK SEL
A
K4128-Slave
A
K4128-Master
A
K4128-Slave
A
K4128-Master
2
3
4
2
3
4
[AKD4129-A]
<KM103600> 2010/06
- 11 -
(2)-2-2-2. OBICK, OLRCK, SDTO AK4129(U1)
JP48
OBICK
JP49
SDTO
JP50
OLRCK
JP46
DIT-OBICK SEL
JP47
DIT-OLRCK SEL
DIT-Slave
DIT-Master
DIT-Slave
DIT-Master
2
3
4
2
3
4
JP18
AK4128-OBICK SEL
JP19
AK4128-OLRCK SEL
A
K4128-Slave
A
K4128-Master
A
K4128-Slave
A
K4128-Master
2
3
4
2
3
4
(2)-2-2-3. 10 (PORT5)
(a) SDTO1 (b)SDTO2 (c)SDTO3
SDTO-SEL
JP17
2
3
4
2
SDTO
1
SDTO-SEL
JP17
2
3
4
2
SDTO
1
SDTO-SEL
JP17
2
3
4
2
SDTO
1
SDTO4
[AKD4129-A]
<KM103600> 2010/06
- 12 -
(3).
[ JP9 (SEL1) ] IMCLKpin
IMCLK DIR 10 MCLK (Default)
GND GND
[ JP10 (ILRCK2-SEL) ] ILRCK2pin
ILRCK2 DIR 10 LRCK2 (Default)
GND GND
[ JP11 (ILRCK3-SEL) ] ILRCK3pin
ILRCK3 DIR 10 LRCK3 (Default)
GND GND
[ JP12 (IBICK3-SEL) ] IBICK3pin
IBICK3 DIR 10 BICK3 (Default)
GND GND
[ JP13 (ILRCK4-SEL) ] ILRCK4pin
ILRCK4
GND GND (Default)
[ JP14 (IBICK4-SEL) ] IBICK4pin
IBICK4
GND GND (Default)
[ JP15 (SEL2) ] INASpin
INAS INAS (Default)
GND GND
[ JP16 (UNLOCK) ] UNLOCKpin LE1
OPEN
SHORT (Default)
[ JP21 (TST0) ] TST0pin – SW17(TST0)
OPEN
SHORT (Default)
[ JP22 (TST1) ] TST1pin – SW3(TST1)
OPEN
SHORT (Default)
[ JP23 (TST2) ] TST2pin – SW3(TST2)
OPEN
SHORT (Default)
[ JP24 (SEL4) ] SDApin
SDA 10 (PORT11, 5 ) – SDA pin (Default)
GND GND
[ JP25 (TST3) ] TST3pin – SW17(TST3)
OPEN
SHORT (Default)
[AKD4129-A]
<KM103600> 2010/06
- 13 -
[ JP31 (EXT-CLK) ] J7(EXT-CLK) IMCLKpin
OPEN J7(EXT-CLK) IMCLKpin
SHORT J7(EXT-CLK) IMCLKpin (Default)
J7(EXT-CLK) IMCLKpin
JP27 ”EXT”
[AKD4129-A]
<KM103600> 2010/06
- 14 -
DIP
(1). AK4129 (U1)
(1)-1. SW3
ON“H”, OFF “L”
SW3
No.
Name ON (“H”) OFF (“L”) Default
1 IDIF2 L
2 IDIF1 H
3 IDIF0
Audio Interface Format Setting for Input PORT
Table 3
L
4 SPB Serial Control Mode Parallel Control Mode L
5 TST1 L
6 TST2
TEST Pin
”L”
L
7 SMSEMI Semi-auto Mode Manual Mode L
8 CAD0 Chip Address 0 bit=”1” Chip Address 0 bit=”0” L
Table 2. SW3 Setting
Mode
IDIF2
pin
IDIF1
pin
IDIF0
pin
SDTI1-4 Format
IBICK
Freq
0 L L L 16bit, LSB justified
≥ 32FSI
1 L L H 20bit, LSB justified
≥ 40FSI
2 L H L 24bit, MSB justified
≥ 48FSI
(Default)
3 L H H 24/16bit, I
2
S Compatible
≥ 48FSI or
32FSI
4 H L L 24bit, LSB justified
≥ 48FSI
5 H L H
6 H H H
Reserved
Table 3. AK4129 Audio Interface Format Setting for Input PORT
[AKD4129-A]
<KM103600> 2010/06
- 15 -
(1)-2. SW4
ON“H”, OFF “L”
SW4
No.
Name ON (“H”) OFF (“L”) Default
1 OBIT1 H
2 OBIT0
Output PORT Audio Interface Format Setting 2
Table 6
H
3 TDM TDM mode Stereo mode L
4 CM2 H
5 CM1 L
6 CM0
Clock Select or Mode Select pin for Output PORT
Table 7
L
7 ODIF1 H
8 ODIF0
Output PORT Audio Interface Format Setting 1
Table 5
L
Table 4. SW4 Setting
Mode
TDM
pin
ODIF1
pin
ODIF0
pin
SDTO1-4 Format
0 L L LSB justified
1 L H (Reserved)
2 H L MSB justified (Default)
3
L
H H I
2
S Compatible
4 L L
5 L H
(Reserved)
6 H L
TDM256 mode
24bit MSB justified
7
H
H H
TDM256 mode
24bit I
2
S Compatible
Table 5. Output PORT Audio Interface Format Setting 1
OBICK Frequency
Mode
TDM
pin
Master / Slave
setting
OBIT1
pin
OBIT0
pin
SDTO
1-4
OLRCK OBICK
MSB
justified,
I
2
S
LSB
justified
0 L L 16bit
≥ 32FSO
1 L H 18bit
≥ 36FSO
2 H L 20bit
≥ 40FSO
3
Slave
(CM2-0 =
“HLL” or
“HHL”)
H H 24bit
Input Input
≥ 48FSO
64FSO
(Default)
4 L L 16bit
5 L H 18bit
6 H L 20bit
7
L
Master
(Not CM2-0 =
“HLL”/“HHL”)
H H 24bit
Output Output 64FSO
8
9
10
11
Slave
(CM2-0 =
“HLL” or
“HHL”)
* *
TDM256
mode
24bit
Input Input 256FSO
12
13
14
15
H
Master
(Not CM2-0 =
“HLL”/“HHL”)
* *
TDM256
mode
24bit
Output Output 256FSO
Table 6. Output PORT Audio Interface Format Setting 2
[AKD4129-A]
<KM103600> 2010/06
- 16 -
Mode
CM2
pin
CM1
pin
CM0
pin
Master /
Slave
OMCLK/XTI
Input
MCKO
Output
FSO
0 L L L Master 256FSO 256FSO
8k ∼ 108kHz
1 L L H Master 384FSO 384FSO
8k ∼ 96kHz
2 L H L Master 512FSO 512FSO
8k ∼ 54kHz
3 L H H Master 768FSO 768FSO
8k ∼ 48kHz
4 H L L Slave
In External Clock
Mode,
1.024MHz~36.864MHz.
In X’tal Mode, X’tal
oscillation frequency.
OMCLK
Input Clock
8k ∼ 216kHz
(Default)
5 H L H Master 128FSO 128FSO
8k ∼ 216kHz
6 H H L
7 H H H
Slave
(Bypass)
Not used. (note)
IMCLK
Input Clock
8k ∼ 216kHz
Table 7. Output PORT Master/Slave/Bypass Mode Control Setting
(1)-3. SW5
ON“H”, OFF “L”
SW4
No.
Name ON (“H”) OFF (“L”) Default
1 INAS
L
2 DITHER Dither ON Dither OFF L
3 SMT1 L
4 SMT0
Soft Mute Timer Setting
Table 9
L
5 DEM0 H
6 DEM1
De-emphasis Filter Setting
Table 10
L
7 PM2 H
8 PM1
Channel Mode Setting
Table 11
L
Table 8. SW5 Setting
SMT1pin SMT0 pin Period FSO=48kHz FSO=96kHz FSO=192kHz
L L 1024/fso 21.3ms 10.7ms 5.3ms
(Default)
L H 2048/fso 42.7ms 21.3ms 10.7ms
H L 4096/fso 85.3ms 42.7ms 21.3ms
H H 8192/fso 170.7ms 85.3ms 42.7ms
Table 9. Soft Mute Cycle Setting
DEM1pin DEM0 pin Mode(SDTI1-4)
L L 44.1kHz
L H OFF (Default)
H L 48kHz
H H 32kHz
Table 10. De-emphasis Filter Setting
[AKD4129-A]
<KM103600> 2010/06
- 17 -
PM2
pin
PM1
pin
PDN
pin
Mode
X’tal
Oscillator
XTI pin
XTO
pin
MCKO
pin
L L L
Pull down
to VSS2-5
L L H
6-channel mode
(AK4126
compatible mode)
Power-down
Input
Hi-z
L H L
Pull down
to VSS2-5
L H H
4-channel mode Power-down
Input
Hi-z
Hi-z
H L L Power-down
Pull down
to VSS2-5
Hi-z L
H L H
6-channel mode
(Original mode)
Normal
operation
Input Output
Normal
operation
(Default)
H H L - - - -
H H H
Not available
- - - -
Table 11. Channel Mode Setting
(1)-4. SW17
ON“H”, OFF “L”
SW17
No.
Name ON (“H”) OFF (“L”) Default
1 TST3 L
2 TST0
TEST Pin
”L”
L
Table 12. SW17 Setting
[AKD4129-A]
<KM103600> 2010/06
- 18 -
(2). AK4114 (U2,U3,U4,U6)
(2)-1. SW6(U2), SW7(U3), SW8(U4), SW9(U5)
ON “H”, OFF “L”
SW6
No.
Name ON (“H”) OFF (“L”) Default
1 DIR1-OCKS1 H
2 DIR1-OCKS0
Master Clock Frequency Setting
Table 16
L
3 DIR1-DIF0 24bit, I
2
S Compatible 24bit, Left justified L
Table 13. SW6 Setting
SW7
No.
Name ON (“H”) OFF (“L”) Default
1 DIR2-OCKS1 H
2 DIR2-OCKS0
Master Clock Frequency Setting
Table 16
L
3 DIR2-DIF0 24bit, I
2
S Compatible 24bit, Left justified L
Table 14. SW7 Setting
SW8
No.
Name ON (“H”) OFF (“L”) Default
1 DIR3-OCKS1 H
2 DIR3-OCKS0
Master Clock Frequency Setting
Table 16
L
3 DIR3-DIF0 24bit, I
2
S Compatible 24bit, Left justified L
Table 15. SW8 Setting
Mode OCKS1 pin OCKS0 pin MCKO1 fs (max)
0 L L 256fs 96 kHz
1 L H 256fs 96 kHz
2 H L 512fs 48 kHz (Default)
3 H H 128fs 192 kHz
Table 16. Master Clock Frequency Setting
[AKD4129-A]
<KM103600> 2010/06
- 19 -
(2)-2. SW16(U6)
ON “H”, OFF “L”
SW16
No.
Name ON (“H”) OFF (“L”) Default
1 DIT-OCKS1 H
2 DIT-OCKS0
Master Clock Frequency Setting
Table 18
L
3 DIT-DIF2 H
4 DIT-DIF1 L
5 DIT-DIF0
Audio Interface Format Setting
Table 19
L
Table 17. Master Clock Frequency Setting
Mode OCKS1 pin OCKS0 pin
MCKO1 fs (max)
0 L L 256fs 96 kHz
1 L H 256fs 96 kHz
2 H L 512fs 48 kHz (Default)
3 H H 128fs 192 kHz
Table 18. Master Clock Frequency Setting
LRCK BICK
Mode
DIF2
pin
DIF1
pin
DIF0
pin
DAUX Format
I/O I/O
0 L L L 24bit, Left justified H/L O 64fs O
1 L L H 24bit, Left justified H/L O 64fs O
2 L H L 24bit, Left justified H/L O 64fs O
3 L H H 24bit, Left justified H/L O 64fs O
4 H L L 24bit, Left justified H/L O 64fs O (Default)
5 H L H 24bit, I
2
S Compatible L/H O 64fs O
6 H H L 24bit, Left justified H/L I 64-128fs I
7 H H H 24bit, I
2
S Compatible L/H I 64-128fs I
Table 19. Audio Interface format Setting
[AKD4129-A]
<KM103600> 2010/06
- 20 -
“H” “L”
[SW1] (AK4129-SMUTE) AK4129 (U1)
“H” AK4129 (U1)
[SW2] (AK4129-PDN) AK4129 (U1)
“L”
“H”
[SW10] (DIR1-PDN) AK4114 (U2)
“L”
“H”
[SW11] (DIR2-PDN) AK4114 (U3)
“L”
“H”
[SW12] (DIR3-PDN) AK4114 (U4)
“L”
“H”
[SW14] (DIT-PDN) AK4114 (U6)
“L”
“H”
LED
[LE1] (UNLOCK) AK4129 (U1) UNLOCK
PDN =”L”
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