[AK4430]
MS1196-J-00 2010/05
- 1 -
AK4430 2Vrms 24 DAC ΔΣ
(SCF)
192kHz Set-Top-Box, AV ,
TV 3.3V 2Vrms
16pin TSSOP
: 8kHz ∼ 192kHz
128
64 2
32 4
24 8 FIR
SCF
2Vrms
I/F : 24 , I
2
S
: 512fs, 768fs or 1152fs
256fs or 384fs 2
128fs or 192fs 4
THD+N: –91dB
Dynamic Range: 104dB
: +3.0 ∼ +3.6V
Ta = -20 to 85°C
: 16pin TSSOP (6.4mm x 5.0mm)
192kHz 24-Bit Stereo
Δ
Σ
DAC with 2Vrms Out
p
ut
AK4430
LRCK
BICK
SDTI
Audio
Data
Interface
MCLK
Δ
Σ
Modulator
AOUTL
8X
Interpolator
SCF
LPF
AOUTR
VDD
VSS1
Control
Interface
Clock
D
ivide
r
Δ
Σ
8X
Interpolator
SCF
LPF
Charge
Pump
CP CN VEE VSS2 CVDD
1μ 1μ
VREFH
SMUTE
D
IF
2.2
μ
Modulator
[AK4430]
MS1196-J-00 2010/05
- 2 -
■
AK4430ET -20 ∼ +85°C 16pin TSSOP (0.65mm pitch)
AKD4430 AK4430
■
6
5
4
3
2
1 CN
CP
MCLK
SMUTE
BICK
SDTI
7
DIF 8
VEE
VSS2
CVDD
VREFH
VSS1
VDD
AOUTL
AOUTR
AK4430
Top
View
11
12
13
14
15
16
10
9
LRCK
■ AK4430 AK4420, AK4424, AK4421, AK4421A
AK4420 AK4424 AK4421 AK4421A AK4430
Power Supply
+4.5 ∼ +5.5V +4.5 ∼ +5.5V +3.0 ∼ +3.6V +3.0 ∼ +3.6V +3.0 ∼ +3.6V
Digital de-emphasis - X - - -
I/F format 24-bit MSB/I²S I²S 24-bit MSB/I²S 24-bit MSB/I²S 24-bit MSB/I²S
Pin out Pin#3 SMUTE DEM SMUTE SMUTE SMUTE
Pin#8 DIF SMUTE DIF DIF* DIF*
Pin#13 DZF DZF DZF DZF VREFH
THD+N -92dB -92dB -92dB (-3dBFS) -92dB -91dB
DR 105dB 105dB 102dB 102dB 104dB
Operating
Temperature
ET: -20 ∼ +85°C
VT: -40 ∼ +85°C
ET: -20 ∼ +85°C ET: -20 ∼ +85°C ET: -20 ∼ +85°C ET: -20 ∼ +85°C
(-: Not available, X: Available)
*: Internal pull up (100kΩ)
[AK4430]
MS1196-J-00 2010/05
- 3 -
No. Pin Name I/O Function
1 CN I
Negative Charge Pump Capacitor Terminal Pin
Connect to CP with a 1.0μF low ESR (Equivalent Series Resistance) capacitor
over all temperature. When this capacitor is polarized, the positive polarity
pin should be connected to the CP pin. Non-polarized capacitors can also be
used.
2 CP I
Positive Charge Pump Capacitor Terminal Pin
Connect to CN with a 1.0μF low ESR (Equivalent Series Resistance)
capacitor over temperature. When this capacitor is polarized, the positive
polarity pin should be connected to the CP pin. Non-polarized capacitors can
also be used.
3 SMUTE I
Soft Mute Enable Pin (Internal pull down: 100kΩ)
“H”: Enable, “L”: Disable
4 MCLK I Master Clock Input Pin
5 BICK I Audio Serial Data Clock Pin
6 SDTI I Audio Serial Data Input Pin
7 LRCK I L/R Clock Pin
8 DIF I
Audio Data Interface Format Pin (Internal pull up: 100kΩ)
“L”: 24-bit MSB Justified, “H”: I
2
S,
9 AOUTR O
Right channel Analog Output Pin
When MCLK or LRCK or BICK stops, outputs VSS(0V, typ).
10 AOUTL O
Left channel Analog Output Pin
When MCLK or LRCK or BICK stops, outputs VSS(0V, typ).
11 VDD -
Power Supply Pin, 3.0V∼3.6V
12 VSS1 -
Ground Pin 1
13 VREFH O
Reference Output Pin
Connect to VSS with a 2.2μF low ESR capacitor over all temperature.
14 CVDD -
Charge Pump Power Supply Pin
15 VSS2 -
Ground Pin 2
16 VEE O
Negative Voltage Output Pin
Connect to VSS2 with a 1.0μF low ESR capacitor over all temperature.
When this capacitor is polarized, the positive polarity pin should be
connected to the VSS2 pin. Non-polarized capacitors can also be used.
Note: All input pins except for the SMUTE and DIF pins should not be left floating.
[AK4430]
MS1196-J-00 2010/05
- 4 -
(VSS1=VSS2=0V; Note 1)
Parameter Symbol min max Units
Power Supply VDD
CVDD
-0.3
-0.3
+4.0
+4.0
V
V
Input Current (any pins except for supplies) IIN -
±10
mA
Input Voltage (Note 3) VIND -0.3 VDD+0.3 V
Ambient Operating Temperature Ta -20 85
°C
Storage Temperature Tstg -65 150
°C
Note 1.
Note 2. VSS1 VSS2
Note 3. SMUTE, MCLK, BICK, LRCK, SDTI, DIF pins
:
(VSS1=VSS2=0V; Note 1)
Parameter Symbol min typ max Units
Power Supply VDD
CVDD
+3.0
VDD
+3.6 V
Note 4. VDD CVDD
:
[AK4430]
MS1196-J-00 2010/05
- 5 -
( Ta = 25°C; VDD=CVDD = +3.3V; fs = 44.1kHz; BICK = 64fs; Signal Frequency = 1kHz; 24bit Input
Data; Measurement frequency = 20Hz ∼ 20kHz; R
L
≥5kΩ)
Parameter min typ max Units
Resolution 24 Bits
Dynamic Characteristics (Note 5)
fs=44.1kHz, BW=20kHz -91 -82 dB
fs=96kHz, BW=40kHz -91 - dB
THD+N
fs=192kHz, BW=40kHz -89 - dB
Dynamic Range (-60dBFS with A-weighted, Note 6) 96 104 dB
S/N (A-weighted, Note 7) 96 104 dB
Interchannel Isolation (1kHz) 90 100 dB
Interchannel Gain Mismatch 0.2 0.5 dB
PSRR (Note 9) 62 dB
DC Accuracy
DC Offset (at output pin) -5 0 +5 mV
Gain Drift 100 -
ppm/°C
Output Voltage (Note 8) 1.85 2.0 2.15 Vrms
Load Capacitance (Note 10) 25 pF
Load Resistance 5
kΩ
Power Supplies
Power Supply Current: (Note 11)
Normal Operation (fs≤96kHz)
Normal Operation (fs=192kHz)
Power-Down Mode (
Note 12)
20
22
10
28
31
100
mA
mA
μA
Note 5. Audio Precision (System Two)
Note 6. 98dB at 16bit data
Note 7. S/N
Note 8. (0dB) VDD
AOUT (typ.@ 0dB) = 2.0Vrms × VDD/3.3.
Note 9. VDD CVDD 1kHz, 50mVpp
Note 10.
Note 11. VDD CVDD
Note 12. (MCLK, BICK, LRCK) VDD VSS
[AK4430]
MS1196-J-00 2010/05
- 6 -
(Ta = 25°C; VDD=CVDD= +3.0 ∼ +3.6V; fs = 44.1kHz)
Parameter Symbol min typ max Units
Digital filter
Passband ±0.05dB (Note 13)
-6.0dB
PB 0
-
22.05
20.0
-
kHz
kHz
Stopband (Note 13) SB 24.1 kHz
Passband Ripple PR
± 0.01
dB
Stopband Attenuation SA 64 dB
Group Delay (Note 14) GD - 24 - 1/fs
Digital Filter + LPF
Frequency Response
20.0kHz
40.0kHz
80.0kHz
fs=44.1kHz
fs=96kHz
fs=192kHz
FR
FR
FR
-
-
-
± 0.05
± 0.05
± 0.05
-
-
-
dB
dB
dB
Note 13. fs ( )
PB=0.4535×fs(@±0.05dB) SB=0.546×fs
Note 14. 16/24
DC
(Ta = 25°C; VDD=CVDD =+3.0 ∼ +3.6V)
Parameter Symbol min typ max Units
High-Level Input Voltage
Low-Level Input Voltage
VIH
VIL
70%VDD
-
-
-
-
30%VDD
V
V
Input Leakage Current (Note 15) Iin - -
± 10 μA
Note 15. SMUTE pin DIF pin SMUTE pin (typ. 100kΩ) DIF pin
(typ. 100kΩ)
[AK4430]
MS1196-J-00 2010/05
- 7 -
(Ta = 25°C; VDD=CVDD = +3.0 ∼ +3.6V)
Parameter Symbol min typ max Units
Master Clock Frequency
Duty Cycle
fCLK
dCLK
4.096
40
-
36.864
60
MHz
%
LRCK Frequency
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Duty Cycle
fsn
fsd
fsq
Duty
8
32
120
45
48
96
192
55
kHz
kHz
kHz
%
Audio Interface Timing
BICK Period
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
BICK Pulse Width Low
Pulse Width High
BICK “↑” to LRCK Edge (
Note 16)
LRCK Edge to BICK “↑” (
Note 16)
SDTI Hold Time
SDTI Setup Time
tBCK
tBCK
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
1/128fsn
1/64fsd
1/64fsq
30
30
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 16. LRCK BICK “↑”
[AK4430]
MS1196-J-00 2010/05
- 8 -
■
1/fCLK
tCLKL
VIH
tCLKH
MCLK
VIL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK
VIL
tBCK
tBCKL
VIH
tBCKH
BICK
VIL
Figure 1. Clock Timing
tLRB
LRCK
VIH
BICK
VIL
tSDS
VIH
SDTI
VIL
tSDH
VIH
VIL
tBLR
Figure 2. Serial Interface Timing
[AK4430]
MS1196-J-00 2010/05
- 9 -
■
MCLK, LRCK, BICK (MCLK) (LRCK)
MCLK ΔΣ
MCLK (
Table 1)
MCLK,LRCK BICK AK4430 0V
(typ) MCLK, LRCK BICK ON
MCLK, LRCK BICK
LRCK MCLK (MHz)
fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs
Sampling
Speed
32.0kHz - - - - 16.3840 24.5760 36.8640
44.1kHz - - - - 22.5792 33.8688 -
48.0kHz - - - - 24.5760 36.8640 -
Normal
32.0kHz 8.192 12.288
44.1kHz 11.2896 16.9344
48.0kHz 12.288 18.432
88.2kHz - - 22.5792 33.8688 - - -
96.0kHz - - 24.5760 36.8640 - - -
Double
176.4kHz 22.5792 33.8688 - - - - -
192.0kHz 24.5760 36.8640 - - - - -
Quad
Table 1.
MCLK= 256fs/384fs 32kHz~96kHz (
Table 2) 32kHz~48kHz
DR, S/N MCLK= 512fs/768fs
MCLK DR,S/N
256fs/384fs 101dB
512fs/768fs 104dB
Table 2. MCLK DR, S/N (fs = 44.1kHz)
■
BICK LRCK SDTI AK4430 2 (
Table 3) DIF
pin MSB 2’s complement BICK
Mode 0 16/20 LSB “0”
Mode DIF pin SDTI Format BICK Figure
0 L
24bit
≥48fs
Figure 3
1 H 24bit I
2
S
≥48fs
Figure 4
Table 3.
[AK4430]
MS1196-J-00 2010/05
- 10 -
LRCK
BICK
(
64fs
)
SDTI
0221 2 24 31 0 1 31 0 1
23:MSB, 0:LSB
22 1 0 Don’t care23
Lch Data Rch Data
23 30 2222423 30
22 1
0 Don’t care
23
2223
Figure 3. Mode 0 Timing
LRCK
BICK
(
64fs
)
SDTI
031 2 24 31 0 1 31 0 1
23:MSB, 0:LSB
22
1
0
Don’t care
23
Lch Data Rch Data
23 25 322423 25
22 1
0
Don’t care23
23
Figure 4. Mode 1 Timing
■
AK4430 (
Figure 5) 2Vrms VSS(0V,typ)
(
Figure 6) Ca Cb 1.0μF ESR(
) CP VSS2
(
Figure 5)
AK4430 VSS(0V,typ)
CVDD
Charge
Pump
CP CN
VSS2
VEE
1uF
1uF
Negative Power
A
K4430
(+)
Cb
Ca
(+)
Figure 5.
[AK4430]
MS1196-J-00 2010/05
- 11 -
A
OUTR
A
K4
4
30
(
AOUTL
)
0V
2Vrms
Figure 6. Audio
■
SMUTE pin “H” Normal Speed Mode 1024LRCK
-∞ (“0”) SMUTE pin “L” -∞ -∞ 1024LRCK
0dB 1024LRCK
0dB
LRCK SMUTE pin 8 “H”
SMUTE pin
Attenuation
1024/fs
0dB
-∞
AOUT
1024/fs
GD GD
(1)
(2)
(3)
:
(1) Normal Speed Mode
1024LRCK (1024/fs) -∞(“0”)
Double Speed Mode
2048LRCK (2048/fs) Quad Speed Mode 4096LRCK
(4096/fs) -∞(“0”)
(2)
(GD)
(3)
1024LRCK Normal Speed Mode
0dB
Figure 7.
[AK4430]
MS1196-J-00 2010/05
- 12 -
■
ON AK4430 MCLK LRCK
“
↑” LRCK
(1)
MCLK 20us
(2) MCLK
2, 3 LRCK
(3)
time A D/A
Time A = 176/fs: Normal speed mode
Time A = 352/fs: Double speed mode
Time A = 704/fs: Quad speed mode
(4)
(5) MCLK pin
“L” VDD 80% min.20us MCLK
Figure 8. System Reset Diagram
D/A Out
(
Analo
g)
MCLK
20 us
Low
Power Supply
(VDD, CVDD)
2, 3
LRCK
Digital
Circuit
Analog
Circuit
Charge Pump
Circuit
Charge Pump
Counter circuit
Time A
(1)
(2)
(3)
Power-up
Power-up
“0” data
D/A In
(
Di
g
ital
)
MUTE
(
D/A Out
)
(4)
(5)
Power down
Power down
Power-up Power down
[AK4430]
MS1196-J-00 2010/05
- 13 -
■
MCLK LRCK BICK AK4430
VSS(0V,typ) MCLK LRCK BICK
Normal Operation
Internal
State
Reset Normal Operation
D/A Out
(Analog)
D/A In
(Digital)
Clock In
MCLK, BICK, LRCK
(2)
VSS
(3)
MCLK or BICK or LRCK
Stop
(4)
(4)
(1)
:
(1) (MCLK,LRCK BICK ) (MCLK, BICK, LRCK)
(2) “0” MCLK LRCK
BICK
(3) 180/fs (Normal speed mode ) GD
(4)
Figure 9.
[AK4430]
MS1196-J-00 2010/05
- 14 -
AK4430
Figure 10 (AKD4430)
Figure 10. Typical Connection Diagram
(1)
ESR
CP, VSS2, VREFH
(2) VSS1, VSS2
(3)
Analog
3.3V
24bit Audio Data
1u (1)
64fs
Master Clock
Analog Ground
Digital Ground
Mode-
Setting
AK4430
DIF
SDTI
BICK
MCLK
SMUTE
CP
CN
LRCK
AOUTR
AOUTL
VDD
VSS1
VREFH
CVDD
VSS2
VEE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
+
+
fs
1u (1)
0.1u
10u
+
0.1u 10u
Lch Out
Rch Out
+
2.2u (1)
+
[AK4430]
MS1196-J-00 2010/05
- 15 -
1.
VDD
CVDD VDD CVDD
VDD CVDD VDD
CVDD VSS
VSS2
2.
VSS(0V,typ) 2.0Vrms(typ, @VDD=3.3V)
ΔΣ ( ) (SCF)
(CTF) 1 LPF(Figure 11)
2’s complement (2 ) 7FFFFFH(@24bit)
800000H(@24bit) 000000H(@24bit) V
AOUT
0V(VSS)
DC ±5 V
AOUT
470
2.2nF
AK4430
2.0Vrms (typ)
Analog
Out
(
= 154kHz, gain = -0.28dB @ 40kHz, gain = -1.04dB @ 80kHz)
Figure 11. External 1
st
order LPF Circuit Example1
[AK4430]
MS1196-J-00 2010/05
- 16 -
0-10°
Detail A
Seating Plane
0.10
0.17±0.05
0.22±0.1
0.65
*5.0±0.1
1.1 (max)
A
1
8
9 16
16pin TSSOP (Unit: mm)
*4.4±0.1
6.4±0.2
0.5±0.2
0.1±0.1
NOTE: Dimension "*" does not include mold flash.
0.13
M
■
: ( )
:
: ( )
[AK4430]
MS1196-J-00 2010/05
- 17 -
AKM
4430ET
XXYYY
1) Pin #1 indication
2) Date Code: XXYYY (5 digits)
XX: Lot#
YYY: Date Code
3) Marketing Code: 4430ET
4) Asahi Kasei Logo
Date (YY/MM/DD) Revision Reason Page Contents
10/05/31 00
[AK4430]
MS1196-J-00 2010/05
- 18 -
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